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Showing results 1 to 11 of 11
PreviewAuthors / EditorsTitleTypeIssue Date
Steininger Andreas - 2016 - Does Cascading Schmitt-Trigger Stages Improve the...pdf.jpgSteininger, Andreas ; Najvirt, Robert; Maier, Jürgen  Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior?Inproceedings Konferenzbeitrag 2016
Maier Juergen - 2019 - Efficient Metastability Characterization for...pdf.jpgMaier, Jürgen  ; Steininger, Andreas Efficient Metastability Characterization for Schmitt-TriggersInproceedings Konferenzbeitrag 2019
Fuegger Matthias - 2018 - A Faithful Binary Circuit Model with Adversarial Noise.pdf.jpgFügger, Matthias ; Maier, Jürgen  ; Najvirt, Robert; Nowak, Thomas ; Schmid, Ulrich A Faithful Binary Circuit Model with Adversarial NoiseInproceedings Konferenzbeitrag 2018
OEhlinger Daniel - 2020 - The involution tool for accurate digital timing and...pdf.jpgÖhlinger, Daniel ; Maier, Jürgen  ; Függer, Matthias ; Schmid, Ulrich  The involution tool for accurate digital timing and power analysisArticle Artikel Sep-2020
OEhlinger Daniel - 2019 - The Involution Tool for Accurate Digital Timing and...pdf.jpgÖhlinger, Daniel ; Maier, Jürgen  ; Függer, Matthias ; Schmid, Ulrich The Involution Tool for Accurate Digital Timing and Power AnalysisInproceedings Konferenzbeitrag 2019
Steininger Andreas - 2016 - The Metastable Behavior of a Schmitt-Trigger.pdf.jpgSteininger, Andreas ; Maier, Jürgen  ; Najvirt, Robert The Metastable Behavior of a Schmitt-TriggerInproceedings Konferenzbeitrag 2016
Maier Juergen - 2017 - Modeling the CMOS Inverter using Hybrid Systems.pdf.jpgMaier, Jürgen  Modeling the CMOS Inverter using Hybrid SystemsBook Buch 2017
Maier Juergen - 2014 - Online test vector insertion - a concurrent built-in...pdf.jpgMaier, Jürgen  Online test vector insertion - a concurrent built-in self-testing (CBIST) approach for asynchronous logicThesis Hochschulschrift 2014
Maier Juergen - 2014 - Online Test Vector Insertion A Concurrent Built-In...pdf.jpgMaier, Jürgen  ; Steininger, Andreas Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous LogicInproceedings Konferenzbeitrag 2014
Maier Juergen - 2019 - Transistor-Level Analysis of Dynamic Delay Models.pdf.jpgMaier, Jürgen  ; Függer, Matthias; Nowak, Thomas; Schmid, UlrichTransistor-Level Analysis of Dynamic Delay ModelsInproceedings Konferenzbeitrag 2019
Paulweber Philipp - 2019 - Unified ASynchronous Circuit Development.pdf.jpgPaulweber, Philipp ; Maier, Jürgen  ; Cortadella, Jordi Unified (A)Synchronous Circuit DevelopmentBook Buch 2019