Digital Modeling of Asynchronous Integrated Circuits

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Primary Data

Project Acronym Projekt Kurzbezeichnung
DMAC
 
Project Title (de) Projekttitel (de)
Digital Modeling of Asynchronous Integrated Circuits
 
Project Title (en) Projekttitel (en)
Digital Modeling of Asynchronous Integrated Circuits
 
Consortium Coordinator Koordinator des Konsortiums
 
Principal Investigator Projektleiter_in
 

Grants

Funder/Funding Agency Fördergeber
FWF - Österr. Wissenschaftsfonds
Grant number Förderkennnummer
P32431-N30
 

Publications

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Date Issued:  [2000 TO 2021]

Results 1-3 of 3 (Search time: 0.003 seconds).

PreviewAuthor(s)TitleTypeIssue Date
1Maier-2021-Gain and Pain of a Reliable Delay Model-am.pdf.jpgMaier, Jürgen Gain and Pain of a Reliable Delay ModelInproceedings Konferenzbeitrag 11-Oct-2021
2Maier-2021-A Composable Glitch-Aware Delay Model-vor.pdf.jpgMaier, Jürgen ; Öhlinger, Daniel ; Schmid, Ulrich ; Függer, Matthias ; Nowak, Thomas A Composable Glitch-Aware Delay ModelInproceedings Konferenzbeitrag 22-Jun-2021
3OEhlinger Daniel - 2020 - The involution tool for accurate digital timing and...pdf.jpgÖhlinger, Daniel ; Maier, Jürgen ; Függer, Matthias ; Schmid, Ulrich The involution tool for accurate digital timing and power analysisArticle Artikel Sep-2020