Knerr, B., Holzer, M., Angerer, C., & Rupp, M. (2010). Slot-Wise Maximum Likelihood Estimation of the Tag Population Size in FSA Protocols. IEEE Transactions on Communications, 58(2), 578–585. https://doi.org/10.1109/tcomm.2010.02.080571 ( reposiTUm)

Knerr, B., Holzer, M., & Rupp, M. (2008). RRES: A Novel Approach to the Partitioning Problem for a Typical Subset of System Graphs. EURASIP Journal on Embedded Systems, 2008, 1–13. http://hdl.handle.net/20.500.12708/168627 ( reposiTUm)

Belanovic, P., Knerr, B., Holzer, M., & Rupp, M. (2006). A Fully Automated Environment for Verification of Virtual Prototypes. EURASIP Journal on Applied Signal Processing, 2006, 1–12. http://hdl.handle.net/20.500.12708/171673 ( reposiTUm)

Holzer, M., Knerr, B., Belanovic, P., & Rupp, M. (2006). Efficient Design Methods for Embedded Communication Systems. EURASIP Journal on Embedded Systems, 2006(ID 64913), 19. http://hdl.handle.net/20.500.12708/171690 ( reposiTUm)

Belanovic, P., Knerr, B., Holzer, M., Sauzon, G., & Rupp, M. (2005). A Consistent Design Methodology for Wireless Embedded Systems. EURASIP Journal on Applied Signal Processing, VOL. 2005(16), 2598–2612. http://hdl.handle.net/20.500.12708/171578 ( reposiTUm)

Knerr, B., Holzer, M., Angerer, C., & Rupp, M. (2008). Slot-by-slot Minimum Squared Error Estimator for Tag Populations in FSA Protocols. In The 2nd Int. EURASIP Workshop on RFID Technology (pp. 1–13). http://hdl.handle.net/20.500.12708/70247 ( reposiTUm)

Holzer, M., Knerr, B., Angerer, C., & Rupp, M. (2008). Early Frame Restart in RFID Systems. In The Second International EURASIP Workshop on RFID Technology. The Second International EURASIP Workshop on RFID Technology, Budapest, Hungary, EU. http://hdl.handle.net/20.500.12708/70222 ( reposiTUm)

Knerr, B., Holzer, M., Angerer, C., & Rupp, M. (2008). Slot-by-slot Maximum Likelihood Estimation of Tag Populations in Framed Slotted Aloha Protocols. In 2008 Int. Symposium on Performance Evaluation of Computer and Telecommunication Systems (pp. 303–308). http://hdl.handle.net/20.500.12708/70248 ( reposiTUm)

Angerer, C., Holzer, M., Knerr, B., & Rupp, M. (2008). A Flexible Dual Frequency Testbed for RFID. In Tridentcom08: proceedings of the 4th International Conference on Testbeds and Research Infrastructures for the Development of Networks and Communities. Tridentcom08: 4th International Conference on Testbeds and Resarch Infrastructures for the Development of Networks & Communities, Innsbruck, Austria. http://hdl.handle.net/20.500.12708/70146 ( reposiTUm)

Knerr, B., Holzer, M., & Rupp, M. (2007). Novel Genome Coding of Genetic Algorithms for the System Partitioning Problem. In 2007 Symposium on Industrial Embedded Systems Proceedings (pp. 134–141). http://hdl.handle.net/20.500.12708/69725 ( reposiTUm)

Holzer, M., Knerr, B., & Rupp, M. (2007). Design Space Exploration with Evolutionary Multi-Objective Optimisation. In 2007 Symposium on Industrial Embedded Systems Proceedings (pp. 126–133). http://hdl.handle.net/20.500.12708/69726 ( reposiTUm)

Angerer, C., Knerr, B., Holzer, M., Adalan, A., & Rupp, M. (2007). Flexible Simulation and Prototyping for RFID Designs. In P. Belanovic (Ed.), The first international EURASIP Workshop on RFID Technology, RFID 2007, Book of Proceedings (pp. 51–54). http://hdl.handle.net/20.500.12708/69784 ( reposiTUm)

Knerr, B., Holzer, M., & Rupp, M. (2007). Restricted Range Exhaustive Search: A New Heuristic for HW/SW Partitioning of Task Graphs. In Proceedings XXII Conference on Design of Circuits and Integrated Systems (pp. 241–246). http://hdl.handle.net/20.500.12708/69924 ( reposiTUm)

Holzer, M., Knerr, B., & Rupp, M. (2007). Design Space Exploration for Real-Time Reconfigurable Computing. In Asilomar Conference on Signals, Systems, and Computers (pp. 1981–1985). http://hdl.handle.net/20.500.12708/69781 ( reposiTUm)

Knerr, B., Holzer, M., & Rupp, M. (2006). A Fast Rescheduling Heuristic of SDF Graphs for HW/SW Partitioning Algorithms. In Proceedings of COMSWARE 2006 (p. 8). http://hdl.handle.net/20.500.12708/69006 ( reposiTUm)

Knerr, B., Holzer, M., & Rupp, M. (2006). Extending the GCLP Algorithm for HW/SW Partitioning: A Detailed Platform Model and Performance Improvements. In Austrochip 2006 Tagungsband (pp. 89–95). http://hdl.handle.net/20.500.12708/69216 ( reposiTUm)

Holzer, M., & Knerr, B. (2006). Pareto Front Generation for a Tradeoff between Area and Timing. In Austrochip 2006 Tagungsband (pp. 131–134). http://hdl.handle.net/20.500.12708/69217 ( reposiTUm)

Holzer, M., Knerr, B., & Rupp, M. (2006). Structural Verification in Minimal Time. In International Symposium on System-on-Chip (pp. 151–154). http://hdl.handle.net/20.500.12708/69281 ( reposiTUm)

Knerr, B., Holzer, M., & Rupp, M. (2006). Improvements Of The Gclp Algorithm For Hw/sw Partitioning Of Task Graphs. In Proceedings of the 4th IASTED International Conference on Circuits, Systems, and Signals (pp. 107–113). http://hdl.handle.net/20.500.12708/69290 ( reposiTUm)

Holzer, M., & Rupp, M. (2006). Static Code Analysis of Functional Descriptions in SystemC. In M. Rupp (Ed.), DELTA 2006 Third IEEE International Workshop on Electronic Design, Test & Applications (pp. 243–248). http://hdl.handle.net/20.500.12708/68991 ( reposiTUm)

Belanovic, P., Holzer, M., Knerr, B., & Rupp, M. (2005). Automated Verification Pattern Refinement for Virtual Prototypes. In Conference of Design of Circuits and Integrated Systems (p. 6). http://hdl.handle.net/20.500.12708/68691 ( reposiTUm)

Knerr, B., Holzer, M., & Rupp, M. (2005). Task Scheduling for Power Optimisation of Multi Frequency Synchronous Data Flow Graphs. In Proceedings of the 18th Annual Symposium on Integrated Circuits and System Design (pp. 50–55). ACM Press. http://hdl.handle.net/20.500.12708/68739 ( reposiTUm)

Holzer, M., & Rupp, M. (2005). Static Estimation of Execution Times for Hardware Accelerators in System-on-Chips. In Proceedings of International Symposium on System-on-Chip 2005 (pp. 62–65). http://hdl.handle.net/20.500.12708/68790 ( reposiTUm)

Holzer, M., Belanovic, P., Knerr, B., & Rupp, M. (2005). Automatic Design Techniques for Embedded Systems. In Proceedings of GI/ITG/GMM Workshop Modellierung und Verifikation (p. 10). http://hdl.handle.net/20.500.12708/68809 ( reposiTUm)

Knerr, B., Holzer, M., & Rupp, M. (2005). Fast Rescheduling of Multi-Rate Systems for HW/SW Partitioning Algorithms. In Proceedings of Thirty-Ninth Annual Asilomar Conference on Signals, Systems, and Computers (pp. 1375–1379). http://hdl.handle.net/20.500.12708/68815 ( reposiTUm)

Holzer, M., Belanovic, P., Knerr, B., & Rupp, M. (2003). Design Methodology for Signal Processing in Wireless Systems. In Informationstagung Mikroelektronik (pp. 303–307). http://hdl.handle.net/20.500.12708/68702 ( reposiTUm)

Rupp, M., Knerr, B., & Holzer, M. (2008). Heuristic Optimisation Methods for System Partitioning in HW/SW Co-Design. Technische Universität Madrid, Madrid, EU. http://hdl.handle.net/20.500.12708/88823 ( reposiTUm)

Angerer, C., & Holzer, M. (2007). Flexible Simulation and Prototyping for RFID Designs. ftw RFID Tutorial, Wien, Austria. http://hdl.handle.net/20.500.12708/88640 ( reposiTUm)

Holzer, M. (2008). Design space exploration for the development of embedded systems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-16769 ( reposiTUm)