Fuchs, G., & Steininger, A. (2011). VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation. Journal of Electrical and Computer Engineering, 2011. https://doi.org/10.1155/2011/936712 ( reposiTUm)

Polzer, T., Handl, T., & Steininger, A. (2009). A Metastability-Free Multi-synchronous Communication Scheme for SoCs. In R. Guerraoui & F. Petit (Eds.), Stabilization, Safety, and Security of Distributed Systems: 11th International Symposium, SSS 2009, Lyon, France, November 3-6, 2009. Proceedings (pp. 578–592). Springer. https://doi.org/10.1007/978-3-642-05118-0_40 ( reposiTUm)

Fuchs, G. (2009). Implications of VLSI Fault Models and Distributed Systems Failure Models --- A Hardware Designer’s View. In Fault-Tolerant Distributed Algorithms on VLSI Chips (p. ?). Leibniz Zentrum Informatik. http://hdl.handle.net/20.500.12708/52888 ( reposiTUm)

Fuchs, G., Függer, M., & Steininger, A. (2009). On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme. In 2009 15th IEEE Symposium on Asynchronous Circuits and Systems. ASYNC 2009 (International Symposium on Asynchronous Circuits and Systems), Chapel Hill, North Carolina, Non-EU. IEEE Computer Society. https://doi.org/10.1109/async.2009.15 ( reposiTUm)

Függer, M., Fuchs, G., & Steininger, A. (2009). On the Stability and Robustness of Non-Synchronous Circuits with Timing Loops. In WSDN 2009 (pp. 45–50). Springer. http://hdl.handle.net/20.500.12708/52868 ( reposiTUm)

Fuchs, G., Függer, M., Schmid, U., & Steininger, A. (2008). Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip. In 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. 11th EUROMICRO Conference on Digital System Design (DSD 2008), Parma, Italien, EU. IEEE. https://doi.org/10.1109/dsd.2008.65 ( reposiTUm)

Grahsl, J., Handl, T., & Steininger, A. (2008). Exploring the Usefulness of the Gate-level Stuck-at Fault Model for Muller C-Elements. In 20. Workshop Testmethoden und Vuverlässigkeit von Schaltungen und Systemen (pp. 165–169). http://hdl.handle.net/20.500.12708/52459 ( reposiTUm)

Handl, T., Steininger, A., & Kempf, G. (2007). An Efficient Test Strategy for a Fault-Tolerant Clock Generator for Systems-on-Chip. In 19. Workshop - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (pp. 66–70). http://hdl.handle.net/20.500.12708/51796 ( reposiTUm)

Grahsl, J., Handl, T., Steininger, A., & Kempf, G. (2007). SAFE - A Scalable Environment for Automated Transistor Level Fault Effect Analysis. In Austrochip - Workshop on Microelectronics (pp. 91–98). http://hdl.handle.net/20.500.12708/52053 ( reposiTUm)

Handl, T., Steininger, A., & Kempf, G. (2007). Adopting the Scan Approach for a Fault Tolerant Asynchronous Clock Generation Circuit. In Proceedings IDT’07 - The Second International Design and Test Workshop (pp. 115–119). http://hdl.handle.net/20.500.12708/52055 ( reposiTUm)

Steininger, A., Handl, T., Fuchs, G., & Zangerl, F. (2006). Testing the Hardware Implementation of a Distributed Clock Generation Algorithm for SoCs. In East-West Design & Test International Workshop (pp. 59–64). http://hdl.handle.net/20.500.12708/51504 ( reposiTUm)

Fuchs, G., Függer, M., Steininger, A., & Zangerl, F. (2006). Analysis of Constraints in a Fault-Tolerant Distributed Clock Generation Scheme. In WDES 2006 3rd Workshop on Dependable Embedded Systems (pp. 22–27). http://hdl.handle.net/20.500.12708/51503 ( reposiTUm)

Fuchs, G., Grahsl, J., Schmid, U., Steininger, A., & Kempf, G. (2006). Threshold Modules -- Die Schlüsselelemente zur Verteilten Generierung eines Fehlertoleranten Taktes. In Austrochip Mikroelektroniktagung (pp. 149–156). http://hdl.handle.net/20.500.12708/51506 ( reposiTUm)

Függer, M., Handl, T., Steininger, A., Widder, J., & Tögel, C. (2006). An Efficient Test for a Transition Signalling based Up-/Down-Counter. In Austrochip Mikroelektroniktagung (pp. 55–62). http://hdl.handle.net/20.500.12708/51505 ( reposiTUm)

Függer, M., Schmid, U., Fuchs, G., & Kempf, G. (2006). Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip. In EDCC-6 (pp. 87–96). http://hdl.handle.net/20.500.12708/51507 ( reposiTUm)

Ferringer, M., Fuchs, G., Steininger, A., & Kempf, G. (2006). VLSI Implementation of a Fault-Tolerant Distributed Clock Generation. In The 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (pp. 563–571). http://hdl.handle.net/20.500.12708/51509 ( reposiTUm)

Steininger, A., Függer, M., Schmid, U., & Fuchs, G. (2006). Fault-Tolerant Algorithms on SoCs - A case study. In Supplement Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN) (pp. 190–191). http://hdl.handle.net/20.500.12708/51508 ( reposiTUm)

Fuchs, G., Schmid, U., & Steininger, A. (2004). Ein Verfahren für das verteilte Generieren eines fehlertoleranten adaptiven Taktes in Hardware. http://hdl.handle.net/20.500.12708/32979 ( reposiTUm)