Conference Proceedings Contributions

Veeravalli, V. S., & Steininger, A. (2016). Study of a Delayed Single-Event Effect in the Muller C-element. In Proc 21st IEEE European Test Symposium. 21st IEEE European Test Symposium, Amsterdam, Netherlands (the). http://hdl.handle.net/20.500.12708/56885 ( reposiTUm)
Veeravalli, V. S., & Steininger, A. (2016). Design and Physical Implementation of a Target ASIC for SET Experiments. In Proc. 2016 Euromicro Conference on Digital System Design (DSD) (pp. 694–697). IEEE. http://hdl.handle.net/20.500.12708/56884 ( reposiTUm)
Veeravalli, V. S., & Steininger, A. (2014). Long term on-chip monitoring of SET pulsewidths in a fully digital ASIC. In 22nd Austrian Workshop on Microelectronics (Austrochip). 22nd Austrian Workshop on Microelectronics, Graz, Austria. IEEE. https://doi.org/10.1109/austrochip.2014.6946318 ( reposiTUm)
Steininger, A., Veeravalli, V. S., Alexandrescu, D., Costenaro, E., & Anghel, L. (2014). Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. In 2014 IEEE 32nd International Conference on Computer Design (ICCD). 2014 32nd IEEE International Conference on Computer Design (ICCD), Seoul, Korea (the Republic of). IEEE. https://doi.org/10.1109/iccd.2014.6974663 ( reposiTUm)