Beiträge in Tagungsbänden

Jordan, A., Brandner, F., & Schoeberl, M. (2013). Static analysis of worst-case stack cache behavior. In Proceedings of the 21st International conference on Real-Time Networks and Systems - RTNS ’13. ACM. https://doi.org/10.1145/2516821.2516828 ( reposiTUm)
Jordan, A., Kim, N., & Krall, A. (2013). IR-level versus machine-level if-conversion for predicated architectures. In Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems - ODES ’13. 10th Workshop on Optimizations for DSP and Embedded Systems, Shenzen, China. ACM. https://doi.org/10.1145/2443608.2443611 ( reposiTUm)
Brandner, F., Pavlu, V., & Krall, A. (2011). Modeling Application-Specific Processors for the Use in Cyber-Physical Systems. In Informatik 2011. 41. Jahrestagung der Gesellschaft für Informatik, Berlin, Deutschland, EU. Gesellschaft für Informatik e.V. (GI). http://hdl.handle.net/20.500.12708/53970 ( reposiTUm)
Barany, G. (2011). Register Reuse Scheduling. In 9th Workshop on Optimizations for DSP and Embedded Systems (ODES-9) (p. 8). http://hdl.handle.net/20.500.12708/53627 ( reposiTUm)
Pavlu, V., Schordan, M., & Krall, A. (2011). Computation of Alias Sets from Shape Graphs for Comparison of Shape Analysis Precision. In Proceedings of the Eleventh IEEE International Workshop on Source Code Analysis and Manipulation (pp. 25–34). IEEE. http://hdl.handle.net/20.500.12708/53969 ( reposiTUm)
Pavlu, V., & Krall, A. (2010). Fast JIT Code Generation for x86-64 with LLVM. In ACACES 2011 Poster Abstracts (pp. 289–290). HiPEAC. http://hdl.handle.net/20.500.12708/53968 ( reposiTUm)
Barany, G., & Prantl, A. (2010). Source-Level Support for Timing Analysis. In Leveraging Applications of Formal Methods, Verification and Validation. 4th International Symposium on Leveraging Applications, ISoLA 2010 (pp. 434–448). Springer. https://doi.org/10.1007/978-3-642-16561-0_40 ( reposiTUm)
Barany, G., & Krall, A. (2010). Optimistic Integrated Instruction Scheduling and Register Allocation. In Proceedings of the Junior Scientist Conference 2010 (pp. 97–98). http://hdl.handle.net/20.500.12708/53123 ( reposiTUm)
Pavlu, V., & Schordan, M. (2010). Measuring Shape Analysis Precision. In Junior Scientist Conference 2010 (pp. 75–76). http://hdl.handle.net/20.500.12708/53124 ( reposiTUm)
Barany, G., & Krall, A. (2010). Optimistic Integrated Instruction Scheduling and Register Allocation. In 15th Workshop on Compilers for Parallel Computing (CPC 2010) (p. 15). http://hdl.handle.net/20.500.12708/53172 ( reposiTUm)
Barany, G., Jordan, A., Pavlu, V., & Krall, A. (2010). Optimal and Heuristic Code Generation for Explicitly Parallel Processors. In ACACES 2010 Poster Abstracts (pp. 87–88). HiPEAC. http://hdl.handle.net/20.500.12708/53173 ( reposiTUm)
Brandner, F., Pavlu, V., & Krall, A. (2010). Execution models for processors and instructions. In NORCHIP 2010. Norchip 2010, Tampere, Finland, EU. IEEE Proceedings. https://doi.org/10.1109/norchip.2010.5669478 ( reposiTUm)

Präsentationen

Jordan, A. (2013). Criticality: Static Profiling for the Worst Case. Google PhD Student Summit on Compiler & Programming Technology 2013, München, Germany. http://hdl.handle.net/20.500.12708/85644 ( reposiTUm)
Barany, G. (2013). Optimal and Heuristic Global Code Motion for Minimal Spilling. POPL 2013: 40th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, Rom, Italy. http://hdl.handle.net/20.500.12708/85543 ( reposiTUm)
Barany, G., & Krall, A. (2010). Optimistic Integrated Instruction Scheduling and Register Allocation. ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems (LCTES 2010), Stockholm, Schweden, EU. http://hdl.handle.net/20.500.12708/84989 ( reposiTUm)