IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Journal description

Title Titel
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
 
e-ISSN
1557-9999
 
ISSN
1063-8210
 
Publisher Herausgeber
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
 
Publisher's Address Herausgeber Adresse
445 HOES LANE, PISCATAWAY, USA, NJ, 08855-4141
 
Listed in SCI Aufgelistet im SCI
 
Peer reviewed Begutachtet
 
 

Publications Publikationen

Results 1-10 of 10 (Search time: 0.002 seconds).

PreviewAuthor(s)TitleTypeIssue Date
1Ghanaatian, Reza ; Balatsoukas-Stimming, Alexios ; Müller, Thomas Christoph ; Meidlinger, Michael ; Matz, Gerald ; Teman, Adam ; Burg, Andreas A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message PassingArtikel Article Feb-2018
2Liu, Shaoteng ; Jantsch, Axel ; Lu, Zhonghai A Fair and Maximal Allocator for Single-Cycle On-Chip Homogeneous Resource AllocationArtikel Article 2014
3Ganjeheizadeh Rohani, Shokat ; Taherinejad, Nima ; Radakovits, David A Semiparallel Full-Adder in IMPLY LogicArtikel Article 2020
4Kanduri, Anil ; Haghbayan, Mohammad-Hashem ; Rahmani, Amir M. ; Liljeberg, Pasi ; Jantsch, Axel ; Tenhunen, Hannu ; Dutt, Nikil Accuracy aware power management for many-core systems running error resilient applicationsArtikel Article 2017
5Marchisio, Alberto ; Mrazek, Vojtech ; Hanif, Muhammad Abdullah ; Shafique, Muhammad FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network AcceleratorsArtikel Article 2021
6Rahmani, Amir ; Haghbayan, Mohammad-Hashem ; Miele, Antonio ; Liljeberg, Pasi ; Jantsch, Axel ; Tenhunen, Hannu Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon EraArtikel Article Feb-2017
7Putra, Rachmad Vidya Wicaksana ; Hanif, Muhammad Abdullah ; Shafique, Muhammad ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network AcceleratorsArtikel Article 2021
8TaheriNejad, Nima SIXOR: Single-cycle In-memristor XORArtikel Article 2021
9Camargo, Vinicius V. A. ; Kaczer, Ben ; Wirth, Gilson ; Grasser, Tibor ; Groeseneken, Guido Use of SSTA Tools for Evaluating BTI Impact on Combinational CircuitsArtikel Article 2013
10Jafari, Fahimeh ; Jantsch, Axel ; Lu, Zhonghai Weighted Round Robin Configuration for Worst-Case Delay Optimization in {N}etwork-on-{C}hipArtikel Article 2016