Analysis & Modeling of Single-Event-Transients in VLSI Chips

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Primary Data

Project Acronym Projekt Kurzbezeichnung
EASET
 
Project Title (de) Projekttitel (de)
Analysis & Modeling of Single-Event-Transients in VLSI Chips
 
Consortium Coordinator Koordinator des Konsortiums
 
Principal Investigator Projektleiter_in
 

Publications

Results 1-4 of 4 (Search time: 0.001 seconds).

PreviewAuthor(s)TitleTypeIssue Date
1Veeravalli, Varadan Savulimedu ; Steininger, Andreas Design and Physical Implementation of a Target ASIC for SET ExperimentsKonferenzbeitrag Inproceedings 2016
2Veeravalli, Varadan Savulimedu ; Steininger, Andreas Study of a Delayed Single-Event Effect in the Muller C-elementKonferenzbeitrag Inproceedings 2016
3Veeravalli, Varadan Savulimedu ; Steininger, Andreas Long term on-chip monitoring of SET pulsewidths in a fully digital ASICKonferenzbeitrag Inproceedings 2014
4Steininger, Andreas ; Veeravalli, Varadan S. ; Alexandrescu, Dan ; Costenaro, Enrico ; Anghel, Lorena Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline exampleKonferenzbeitrag Inproceedings 2014