<div class="csl-bib-body">
<div class="csl-entry">Ghanaatian, R., Balatsoukas-Stimming, A., Müller, T. C., Meidlinger, M., Matz, G., Teman, A., & Burg, A. (2018). A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing. <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, <i>26</i>(2), 329–340. https://doi.org/10.1109/tvlsi.2017.2766925</div>
</div>
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dc.identifier.issn
1063-8210
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dc.identifier.uri
http://hdl.handle.net/20.500.12708/146104
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dc.description.abstract
An ultrahigh throughput low-density parity-check (LDPC) decoder with an unrolled full-parallel architecture is proposed, which achieves the highest decoding throughput compared to previously reported LDPC decoders in the literature. The decoder benefits from a serial message-transfer approach between the decoding stages to alleviate the well-known routing congestion problem in parallel LDPC decoders. Furthermore, a finite-alphabet message passing algorithm is employed to replace the VN update rule of the standard min-sum (MS) decoder with lookup tables, which are designed in a way that maximizes the mutual information between decoding messages. The proposed algorithm results in an architecture with reduced bit-width messages, leading to a significantly higher decoding throughput and to a lower area compared to an MS decoder when serial message transfer is used. The architecture is placed and routed for the standard MS reference decoder and for the proposed finite-alphabet decoder using a custom pseudo-hierarchical backend design strategy to further alleviate routing congestions and to handle the large design. Postlayout results show that the finite-alphabet decoder with the serial message-transfer architecture achieves a throughput as large as 588 Gb/s with an area of 16.2 mm 2 and dissipates an average power of 22.7 pJ per decoded bit in a 28-nm fully depleted silicon on isulator library. Compared to the reference MS decoder, this corresponds to 3.1 times smaller area and 2 times better energy efficiency.
en
dc.language.iso
en
-
dc.publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
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dc.relation.ispartof
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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dc.subject
Electrical and Electronic Engineering
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dc.subject
Software
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dc.subject
Hardware and Architecture
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dc.title
A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing
en
dc.type
Artikel
de
dc.type
Article
en
dc.description.startpage
329
-
dc.description.endpage
340
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dc.type.category
Original Research Article
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tuw.container.volume
26
-
tuw.container.issue
2
-
tuw.journal.peerreviewed
true
-
tuw.peerreviewed
true
-
wb.publication.intCoWork
International Co-publication
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tuw.researchTopic.id
I7
-
tuw.researchTopic.name
Telecommunication
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tuw.researchTopic.value
100
-
dcterms.isPartOf.title
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
-
tuw.publication.orgunit
E389-03 - Forschungsbereich Signal Processing
-
tuw.publisher.doi
10.1109/tvlsi.2017.2766925
-
dc.identifier.eissn
1557-9999
-
dc.description.numberOfPages
12
-
tuw.author.orcid
0000-0002-0643-7866
-
tuw.author.orcid
0000-0002-3944-9855
-
tuw.author.orcid
0000-0003-1784-806X
-
tuw.author.orcid
0000-0002-8233-4711
-
wb.sci
true
-
wb.sciencebranch
Elektrotechnik, Elektronik, Informationstechnik
-
wb.sciencebranch.oefos
2020
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wb.facultyfocus
Telekommunikation
de
wb.facultyfocus
Telecommunications
en
wb.facultyfocus.faculty
E350
-
item.fulltext
no Fulltext
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item.grantfulltext
restricted
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item.languageiso639-1
en
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item.openairetype
research article
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item.cerifentitytype
Publications
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item.openairecristype
http://purl.org/coar/resource_type/c_2df8fbb1
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crisitem.author.dept
E389 - Telecommunications
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crisitem.author.dept
E389-03 - Forschungsbereich Signal Processing
-
crisitem.author.dept
E350 - Fakultät für Elektrotechnik und Informationstechnik
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crisitem.author.orcid
0000-0003-1784-806X
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crisitem.author.parentorg
E350 - Fakultät für Elektrotechnik und Informationstechnik