<div class="csl-bib-body">
<div class="csl-entry">Xu, D., Ningmei, Y., Huang, H., Pudukotai Dinakarrao, S. M., & Yu, H. (2017). Q-Learning-Based Voltage-Swing Tuning and Compensation for 2.5-D Memory-Logic Integration. <i>IEEE Design and Test</i>, <i>35</i>(2), 91–99. https://doi.org/10.1109/mdat.2017.2764075</div>
</div>
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dc.identifier.issn
2168-2356
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dc.identifier.uri
http://hdl.handle.net/20.500.12708/146891
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dc.description.abstract
In this paper, an I/O management with Q-Learning based Transmitter Swing Adjustment and Receiver Compensation is developed for an energy-efficient 2.5D memory-logic integration. Instead of transmitting signal with fixed large voltage swing, a Q-learning algorithm and receiver signal compensation mechanism are deployed to adaptively adjust the I/O output-voltage swing, so as to leverage the trade-off between the power reduction and bit error rate (BER). Simulation results show that the proposed adaptive 2.5D I/Os (in 65nm CMOS) can achieve an average of 13mW I/O power, 4GHz bandwidth and 3:25pJ=bit energy efficiency for one channel under 10^-6 BER. With the use of Q-learning and further receiver compensation, we can achieve 12.95% and 15.61% power reduction and 14% energy efficiency improvement compared to the use of constant output-voltage swing based I/O communication.
en
dc.language.iso
en
-
dc.publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
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dc.relation.ispartof
IEEE Design and Test
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dc.subject
Electrical and Electronic Engineering
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dc.subject
Software
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dc.subject
Hardware and Architecture
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dc.subject
Q-learning
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dc.subject
Through-silicon interposer (TSI)
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dc.subject
memory-logic integration
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dc.subject
voltage-swing tuning
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dc.subject
receiver compensation
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dc.subject
low power I/O
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dc.title
Q-Learning-Based Voltage-Swing Tuning and Compensation for 2.5-D Memory-Logic Integration
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dc.type
Artikel
de
dc.type
Article
en
dc.description.startpage
91
-
dc.description.endpage
99
-
dc.type.category
Original Research Article
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tuw.container.volume
35
-
tuw.container.issue
2
-
tuw.journal.peerreviewed
true
-
tuw.peerreviewed
true
-
wb.publication.intCoWork
International Co-publication
-
tuw.researchTopic.id
I1
-
tuw.researchTopic.id
C5
-
tuw.researchTopic.id
C3
-
tuw.researchTopic.name
Logic and Computation
-
tuw.researchTopic.name
Computer Science Foundations
-
tuw.researchTopic.name
Computational System Design
-
tuw.researchTopic.value
40
-
tuw.researchTopic.value
20
-
tuw.researchTopic.value
40
-
dcterms.isPartOf.title
IEEE Design and Test
-
tuw.publication.orgunit
E384-02 - Forschungsbereich Systems on Chip
-
tuw.publisher.doi
10.1109/mdat.2017.2764075
-
dc.identifier.eissn
2168-2364
-
dc.description.numberOfPages
9
-
tuw.author.orcid
0000-0002-1870-1740
-
tuw.author.orcid
0000-0002-2533-2082
-
wb.sci
true
-
wb.sciencebranch
Elektrotechnik, Elektronik, Informationstechnik
-
wb.sciencebranch
Informatik
-
wb.sciencebranch.oefos
2020
-
wb.sciencebranch.oefos
1020
-
wb.facultyfocus
System- und Automatisierungstechnik
de
wb.facultyfocus
System and Automation Engineering
en
wb.facultyfocus.faculty
E350
-
item.grantfulltext
none
-
item.openairecristype
http://purl.org/coar/resource_type/c_2df8fbb1
-
item.openairetype
research article
-
item.languageiso639-1
en
-
item.cerifentitytype
Publications
-
item.fulltext
no Fulltext
-
crisitem.author.dept
E384 - Institut für Computertechnik
-
crisitem.author.parentorg
E350 - Fakultät für Elektrotechnik und Informationstechnik