Optimization of advanced, high-speed DRAM input-output circuits

Abstract

Computer systems gain performance from year to year. New operating systems and applications increase the demand on processing speed and memory.<br />The memory density in a computer system doubles every two years. Data rates between CPU and DRAM memory also have to increase and will reach 6:4Gb=s per bit-line in the year 2013. Computer manufacturers try to keep their systems as cheap as possible and don't want to introduce new interfaces as long as possible.<br />It is planned to transmit data rates in the range of 10Gb=s and more over legacy motherboard-DIMM channels. High Inter-Symbol-Interference (ISI) will lead to the integration of equalization circuits at the high-speed memory interface.<br />In this work predistortion circuits used at the transmitter and equalization circuits used at the receiver are presented. Predistortion and equalization circuits are optimized for the CPU-DRAM interface looking at three main requirements.<br />First the reduction of ISI up to data rates of 10Gb=s with equalization tted to the DRAM channel characteristics. Second, with respect to dierent technologies.<br />CMOS-technology with good performance is used at CPU side and a cheap DRAM-technology with lower performance is used at the DRAM side. Third, the DRAM interface is trimmed to low latency. Predistortion and equalization circuits have to be designed with respect to low latency.<br />Transmitter and receiver circuits applying predistortion and equalization are presented. The chips are fabricated in CMOS and DRAM-technology. The performance of the transmitter and receiver circuits is demonstrated with measurement results applying the chips on a DRAM channel.