A Low-Noise Low-Power Inductor-Less Self- Biased 50 Gbps TIA in 130nm SiGe BiCMOS

Abstract

This paper presents a 50 Gbps voltage-mode TIA topology that uses two paths to output to propose a self-biased and current-reuse TIA. By this, the power consumption and noise are significantly reduced. It also leads to a robust design since power hungry bipolar transistors complicate the biasing circuit design. Compared to current-mode TIAs, the trade-off between BW and a large photodiode capacitance at the input is avoided. The TIA in this paper by RC-degeneration not only breaks the above trade-off but proposes in addition an inductor-less wideband TIA in 130nm SiGe BiCMOS technology. By consuming 7. 3mW, the TIA has 34. S GHz BW a transimpedance gain of 63 dBΩ and 11.3 pA/√Hz input-referred noise for a 150fF parasitic capacitance at the input.