Preliminary Performance and Memory Access Scalability Study of Thick Control Flow Processors

Abstract

Scalability of performance and memory bandwidth over a wide variety of computational and memory access patterns are important goals of multicore processor design. Current commercial processor lines are, however, not succeeding well in meeting key requirements for efficient parallel execution in their small, entry-level designs nor tolerating increasing latency of shared memory accesses, retaining memory access bandwidth per core and keeping the cost of synchronization low as the number of processor cores increases towards high-end products. We have introduced the thick control flow processor architecture (TPA), which combines an advanced shared memory abstraction architecture with the thick control flow (TCF) programming scheme and shown that it can address these requirements in its entry-level configuration. In this paper, we study the performance and memory access scalability of TCF processors. For that we measure the execution time of a number of parallel kernel programs and access patterns over a range of TPA processor configurations and compare them against each other and Intel Skylake-class client and server processors. The results indicate excellent scaling in both execution speed of kernels and bandwidth of memory access.