Loading Effect during SiGe/Si Stack Selective Isotropic Etching for Gate-All-Around Transistors

Abstract

The loading effect hinders the precise profile control during the selective etching of SiGe in stacked SiGe/Si layers, thereby hindering optimal gate-all-around (GAA) transistor performance. In this article, we present a systematic study on the loading effect in the selective isotropic etching of SiGe in SiGe/Si stacks by varying the structure density and process conditions, including chamber pressure and etch time. We measure the lateral SiGe etching depth at different locations within the stack pillars and evaluate the local etch uniformity. The results demonstrate that pressure plays an important role in affecting the isotropic lateral etching performance. Within the tested 10-40 mTorr range, higher pressures lead to increased etch rates but at the cost of reduced uniformity. A noteworthy observation is that the uniformity also decreases as the process time increases. To understand and quantify the phenomena, we propose a physical etch model based on top-down Monte Carlo ray tracing and simulate the etch profiles. We calibrate the model with measured data on less dense pillar arrays with 100 nm spacing and achieve small prediction error on denser pillars with a spacing of 50 nm. The good agreement between simulations and experiments demonstrates that the restriction of particle diffusion in the narrow gap is the major contributor to the loading effect, and our model is capable of quantitatively characterizing this phenomenon by predicting the lateral etching profile. This research provides valuable insights into the etching effects through experiments and theoretical studies in order to promote the advanced etching technology development toward GAA transistor manufacturing.