Electromigration Reliability of Buried Power Rails in Vertically Stacked Devices

Abstract

We apply a compact model for electromigration (EM) to study the build-up of vacancy-induced stress in a buried power rail (BPR) for vertically stacked complementary field-effect transistor (CFET) devices. We observe the highest impact of EM in the M1 copper line, at its interface with a ruthenium interconnect. We further note that the presence of a TiN barrier results in a slight increase in the EM stress. This stress saturates at a relatively low level, likely due to back-migration resulting from the short-length effect (SLE). Vacancy accumulation, which is formed due to EM is primarily counter-driven by stress migration due to high stress gradients. Therefore, the relatively small height of the copper line, at 25nm, prevents the build-up of very high stresses, which ultimately helps limit further vacancy accumulation and stress. In addition, we study how the presence of grains in the copper line impacts the EM behavior, noting that stress increases as the grain sizes decrease.