Temperature Dependent Mismatch and Variability in a Cryo-CMOS Array with 30k Transistors

Abstract

Integrating CMOS circuits and qubits at cryogenic temperatures is one of the key challenges to mitigate wiring constraints and ensure signal integrity to enable up-scaling of quantum computers. While operating in the GHz-regime, interfaces between classical and quantum circuits need to maintain ultra-low power consumption together with very low noise figures. One approach to reduce power consumption is to optimize designs towards operation at lower supply voltages. However, this reduces the tolerable margins on variability and device to device variations. In this study, we present the time-zero variability and mismatch of thousands of nMOS transistors measured from room temperature down to 4 K. We investigate the physical origins of subthreshold variations at cryogenic temperatures and discuss the correlations between transistor parameters. We estimate the influence of different sources on the on-current variability and observe that another source of mismatch, most likely contact resistance, is becoming more important at low temperatures.