<div class="csl-bib-body">
<div class="csl-entry">Seyedfaraji, S., Jager, S., Shakibhamedan, S., Aftab, A., & Rehman, S. (2024). OPTIMA: Design-Space Exploration of Discharge-Based In-SRAM Computing: Quantifying Energy-Accuracy Trade-offs. In <i>DAC ’24: Proceedings of the 61st ACM/IEEE Design Automation Conference</i> (pp. 1–6). Association for Computing Machinery. https://doi.org/10.1145/3649329.3661852</div>
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dc.identifier.uri
http://hdl.handle.net/20.500.12708/214059
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dc.description.abstract
In-SRAM computing promises energy efficiency, but circuit nonlinearities and PVT variations pose major challenges in designing robust accelerators. To address this, we introduce OPTIMA, a modeling framework that aids in analyzing bitline discharge and power consumption in 6T-SRAM-based accelerators. It provides insights into limiting factors and enables fast design-space exploration of circuit configurations. Leveraging OPTIMA for in-SRAM multiplications exhibits ∼100 × simulation speed-up while maintaining an RMS modeling error of 0.88 mV. Exploration yields an optimized multiplier with 1.05 pJ energy consumption per 4-bit operation and classification accuracies of 71.8% (top-1) and 90.4% (top-5) for ImageNet and 92.5% for CIFAR-10 datasets respectively when applied in quantized DNNs. To further support research and development efforts, we have made our OPTIMAptima tool flow available as open source [https://github.com/sevjaeg/optima].
en
dc.language.iso
en
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dc.subject
Deep Neural Networks
en
dc.subject
Image Classification
en
dc.subject
in-memory computing
en
dc.subject
Open source
en
dc.subject
processing-in-memory
en
dc.subject
SRAM
en
dc.title
OPTIMA: Design-Space Exploration of Discharge-Based In-SRAM Computing: Quantifying Energy-Accuracy Trade-offs
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dc.type
Inproceedings
en
dc.type
Konferenzbeitrag
de
dc.contributor.affiliation
TU Wien, Austria
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dc.relation.isbn
9798400706011
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dc.description.startpage
1
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dc.description.endpage
6
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dc.type.category
Full-Paper Contribution
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tuw.booktitle
DAC '24: Proceedings of the 61st ACM/IEEE Design Automation Conference
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tuw.peerreviewed
true
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tuw.relation.publisher
Association for Computing Machinery
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tuw.relation.publisherplace
New York
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tuw.book.chapter
331
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tuw.researchTopic.id
I1
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tuw.researchTopic.id
C6
-
tuw.researchTopic.id
C3
-
tuw.researchTopic.name
Logic and Computation
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tuw.researchTopic.name
Modeling and Simulation
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tuw.researchTopic.name
Computational System Design
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tuw.researchTopic.value
30
-
tuw.researchTopic.value
30
-
tuw.researchTopic.value
40
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tuw.publication.orgunit
E384-02 - Forschungsbereich Systems on Chip
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tuw.publication.orgunit
E056-10 - Fachbereich SecInt-Secure and Intelligent Human-Centric Digital Technologies