Slow-Slope Reset Scheme for Highly-Sensitive CMOS Integrate-and-Dump Receiver OEIC

Abstract

This paper presents a slow-slope reset scheme that reduces charge injection for highly-sensitive integrate-and-dump direct detection receivers. The monolithic receiver OEIC utilizes a source-follower front-end and low-capacitance PIN photodiode, to achieve high sensitivity at higher data rates (250 Mbit/s) than previous ultra-sensitive PIN receivers. Both, the slow-slope and classical rectangular reset scheme, are fabricated with the same front-end, on the same wafer, in 180 nm high-voltage CMOS. The measured transient voltages are in agreement with theory and suggest effective mitigation of charge injection by the slow-slope reset. Using correlated double sampling (CDS), our improved receiver achieves a sensitivity of -47.0 dBm at 250 Mbit/s with 50% return-to-zero (RZ) on-off keying (OOK) modulation and -53.5 dBm at 100 Mbit/s with 80% RZ OOK modulation, both for the reference bit error probability (BER) of 0.002 and wavelength 642 nm. The difference to the shot noise quantum limit at 250 Mbit/s (100 Mbit/s) is 19.7 dB (17.2 dB). In addition, we show that low charge injection enables single sampling, with sensitivities around 1 dB worse than CDS.