Impact of Charge Trapping at Defects on the Robustness of Electronic Circuits

Abstract

Charge trapping at oxide defects is a significant reliability issue in MOS transistors and becomes even more prominent in scaled technology nodes. As devices shrink, the impact of charge capture and emission events of oxide and interface defects on performance becomes more severe. Our work demonstrates how charge trapping affects variability in scaled Silicon and 2D technologies, highlighting the necessity of low trap density to achieve high yield and ensure robust electronic circuit designs.