A Low-Resource Hardware Design for Bearing Fault Detection Using Support Vector Machines

Abstract

Bearing fault detection is critical for ensuring the reliability of industrial machinery, as mechanical failures can lead to significant downtime and maintenance costs. This paper presents a hardware-efficient accelerator for bearing fault detection based on Support Vector Machines (SVMs). Unlike neural network–based accelerators, which are often over-parameterized and demand substantial hardware resources, the proposed design focuses on compactness and hardware efficiency. By combining carefully selected time-domain features with quantization and normalization techniques, we developed a hardware-efficient architecture suitable for both FPGA and ASIC implementation. Evaluated on the Case Western Reserve University (CWRU) bearing dataset, the accelerator achieves 96.93% accuracy in the single-variate and 98.42% in the multi-variates implementation. The FPGA implementation and the ASIC synthesized in TSMC 65-nm demonstrate significantly lower hardware requirements compared to state-of-the-art designs, making the proposed approach highly suitable for deployment in resource-constrained environments.