An efficient SPICE framework for simulation of BTI effects at the circuit level

Abstract

Bias temperature instability (BTI) due to charge trapping at defect sites and defect generation is a major reliability concern in robust analog and digital circuits. Incorporating accurate BTI degradation into circuit-level simulations that captures recovery history and workload dependence remains challenging, because many existing modeling approaches either lack sufficient physical fidelity or suffer from poor computational efficiency. Extensive transistor reliability studies have established that BTI is due to a combination of charge trapping/detrapping and the creation of quasi-permanent interface defects. Regarding charge trapping, it has been shown that the two-state defect model based on non-radiative multiphonon (NMP) theory provides one of the most accurate descriptions under arbitrary mission profiles. However, the comparatively high computational cost of recent NMP implementations limits their applicability in circuit simulations. In this work, we employ the open-source SPICE simulator ngspice and implement an NMP-based defect model that enables computationally efficient emulation of BTI effects at circuit level. To demonstrate its efficiency, we simulate a 501-stage ring oscillator and an operational amplifier with devices containing up to several thousand individual traps. While recent implementations have resulted in an increase of two orders of magnitude in computational cost for only a few hundred traps, our implementation introduces an overhead of less than one order of magnitude even when several thousand defects are included. This modest computational cost, combined with the high physical accuracy of our approach, paves the way to verification across diverse operating conditions as part of the design process, supporting high yield.