<div class="csl-bib-body">
<div class="csl-entry">Maier, J., Függer, M., Nowak, T., & Schmid, U. (2019). Transistor-Level Analysis of Dynamic Delay Models. In <i>2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)</i>. IEEE. https://doi.org/10.1109/ASYNC.2019.00019</div>
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The final publication is available via <a href="https://doi.org/10.1109/ASYNC.2019.00019" target="_blank">https://doi.org/10.1109/ASYNC.2019.00019</a>.
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dc.description.abstract
Delay estimation is a crucial task in digital circuit design as it provides the possibility to assure the desired functionality, but also prevents undesired behavior very early. For this purpose elaborate delay models like the Degradation Delay Model (DDM) and the Involution Delay Model (IDM) have been proposed in the past, which facilitate accurate dynamic timing analysis: Both use delay functions that determine the delay of the current input transition based on the time difference T to the previous output one. Currently, however, extensive analog simulations are necessary to determine the (parameters of the) delay function, which is a very time-consuming and cumbersome task and thus limits the applicability of these models. In this paper, we therefore thoroughly investigate the characterization procedures of a CMOS inverter on the transistor level in order to derive analytical expressions for the delay functions. Based on reasonably simple transistor models we identify three operation regions, each described by a different estimation function. Using simulations with two independent technologies, we show that our predictions are not only accurate but also reasonably robust w.r.t. variations. Our results furthermore indicate that the exponential fitting proposed for DDM is actually only partially valid, while our analytic approach can be applied on the whole range. Even the more complex IDM is predicted reasonably accurate.
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dc.description.sponsorship
Fonds zur Förderung der Wissenschaftlichen Forschung
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dc.description.sponsorship
Fonds zur Förderung der Wissenschaftlichen Forschung
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dc.language
English
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dc.language.iso
en
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dc.publisher
IEEE
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dc.rights.uri
http://rightsstatements.org/vocab/InC/1.0/
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dc.subject
Circuit models
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dc.subject
glitch propagation
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dc.subject
delay models
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dc.subject
pulse degradation
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dc.subject
model parameterization
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dc.title
Transistor-Level Analysis of Dynamic Delay Models
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dc.type
Inproceedings
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dc.type
Konferenzbeitrag
de
dc.rights.license
Urheberrechtsschutz
de
dc.rights.license
In Copyright
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dc.relation.publication
2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
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dc.contributor.affiliation
Université Paris-Sud, France
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dc.relation.isbn
9781538647479
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dc.relation.grantno
P26436
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dc.relation.grantno
S11405
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dc.rights.holder
2019 IEEE
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dc.type.category
Full-Paper Contribution
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dc.publisher.place
Hirosaki, Japan
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tuw.relation.publisherplace
Hirosaki, Japan
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tuw.version
am
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tuw.publication.orgunit
E191 - Institut für Computer Engineering
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tuw.publisher.doi
10.1109/ASYNC.2019.00019
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dc.identifier.libraryid
AC15666408
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dc.identifier.urn
urn:nbn:at:at-ubtuw:3-10181
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tuw.author.orcid
0000-0002-0965-5746
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tuw.author.orcid
0000-0001-9831-8583
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dc.rights.identifier
Urheberrechtsschutz
de
dc.rights.identifier
In Copyright
en
item.openaccessfulltext
Open Access
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item.languageiso639-1
en
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item.openairecristype
http://purl.org/coar/resource_type/c_5794
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item.fulltext
with Fulltext
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item.cerifentitytype
Publications
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item.grantfulltext
open
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item.openairetype
conference paper
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crisitem.author.dept
E191-02 - Forschungsbereich Embedded Computing Systems
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crisitem.author.dept
E182 - Institut für Technische Informatik
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crisitem.author.dept
Université Paris-Sud, France
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crisitem.author.dept
E191-02 - Forschungsbereich Embedded Computing Systems