<div class="csl-bib-body">
<div class="csl-entry">Sodsong, W., Mittermayr, R., Park, Y., Burgstaller, B., & Blieberger, J. (2017). Lazy Parallel Kronecker Algebra-Operations on Heterogeneous Multicores. In F. F. Rivera, T. F. Pena, & J. C. Cabaleiro (Eds.), <i>Euro-Par 2017: Parallel Processing Workshops</i> (pp. 538–552). LNCS / Springer Verlag. https://doi.org/10.1007/978-3-319-64203-1_39</div>
</div>
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dc.identifier.isbn
9783319642031
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dc.identifier.isbn
9783319642024
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dc.identifier.uri
http://hdl.handle.net/20.500.12708/56929
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dc.description.abstract
Kronecker algebra is a matrix calculus which allows the generation of thread interleavings from the source-code of a program. Thread interleavings have been shown effective for proving the absence of deadlocks. Because the number of interleavings grows exponentially in the number of threads, deadlock analysis is still a challenging problem. To make the computation of thread interleavings tractable, we propose a lazy, parallel evaluation method for Kronecker algebra. Our method incorporates the constraints induced by synchronization constructs. To reduce problem size, only interleavings legal under the locking behavior of a program are considered. We leverage the data-parallelism of Kronecker sum- and product-operations for multicores and GPUs. Proposed algebraic transformations further improve performance. For one synthetic and two real-world benchmarks, our GPU implementation is up to 5453× faster than our multi-threaded version. Lazy evaluation significantly reduces memory consumption compared to both the sequential and the multicore versions of the SPIN model-checker.
en
dc.description.sponsorship
Fonds zur Förderung der wissenschaftlichen Forschung (FWF)
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dc.language.iso
en
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dc.publisher
LNCS / Springer Verlag
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dc.relation.ispartofseries
Lecture Notes in Computer Science
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dc.subject
Kronecker algebra
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dc.subject
Lazy evaluation
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dc.subject
Deadlock detection
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dc.subject
Heterogeneous multicores
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dc.subject
GPUs
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dc.title
Lazy Parallel Kronecker Algebra-Operations on Heterogeneous Multicores
en
dc.type
Konferenzbeitrag
de
dc.type
Inproceedings
en
dc.relation.publication
Euro-Par 2017: Parallel Processing Workshops
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dc.relation.isbn
978-3-319-64202-4
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dc.relation.doi
10.1007/978-3-319-64203-1
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dc.relation.issn
0302-9743
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dc.description.startpage
538
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dc.description.endpage
552
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dc.relation.grantno
I1035-N23
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dc.type.category
Full-Paper Contribution
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dc.relation.eissn
1611-3349
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dc.publisher.place
10417 / Santiago de Compostela, Spain
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tuw.booktitle
Euro-Par 2017: Parallel Processing Workshops
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tuw.peerreviewed
true
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tuw.book.ispartofseries
Lecture Notes in Computer Science
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tuw.relation.publisher
Springer
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tuw.relation.publisherplace
Cham
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tuw.project.title
Static Analysis and Just-in-Time Compilation Support for Heterogeneous Multicore Architectures
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tuw.researchTopic.id
I2
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tuw.researchTopic.name
Computer Engineering and Software-Intensive Systems
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tuw.researchTopic.value
100
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tuw.publication.orgunit
E191-03 - Forschungsbereich Automation Systems
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tuw.publisher.doi
10.1007/978-3-319-64203-1_39
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dc.description.numberOfPages
15
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tuw.editor.orcid
0000-0002-7622-4698
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tuw.event.name
Euro-Par 2017 23rd International European Conference on Parallel and Distributed Computing
en
tuw.event.startdate
28-08-2017
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tuw.event.enddate
01-09-2017
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tuw.event.online
On Site
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tuw.event.type
Event for scientific audience
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tuw.event.place
Santiago de Compostela
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tuw.event.country
ES
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tuw.event.presenter
Sodsong, Wasuwee
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wb.sciencebranch
Informatik
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wb.sciencebranch.oefos
1020
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wb.facultyfocus
Computer Engineering (CE)
de
wb.facultyfocus
Computer Engineering (CE)
en
wb.facultyfocus.faculty
E180
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wb.presentation.type
science to science/art to art
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item.openairetype
conference paper
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item.openairecristype
http://purl.org/coar/resource_type/c_5794
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item.fulltext
no Fulltext
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item.grantfulltext
none
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item.languageiso639-1
en
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item.cerifentitytype
Publications
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crisitem.project.funder
FWF Fonds zur Förderung der wissenschaftlichen Forschung (FWF)