Name Card

Full name Familienname, Vorname
Maier, Jürgen
 
Main Affiliation Organisations­zuordnung
 

Own Publications Eigene Publikationen

Results 1-20 of 23 (Search time: 0.001 seconds).

PreviewAuthor(s)TitleTypeIssue Date
1Ferdowsi, Arman ; Maier, Jurgen ; Öhlinger, Daniel ; Schmid, Ulrich A Simple Hybrid Model for Accurate Delay Modeling of a Multi-Input GateInproceedings Konferenzbeitrag 2022
2Maier-2021-Gain and Pain of a Reliable Delay Model-am.pdf.jpgMaier, Jürgen Gain and Pain of a Reliable Delay ModelInproceedings Konferenzbeitrag 11-Oct-2021
3Maier-2021-A Composable Glitch-Aware Delay Model-vor.pdf.jpgMaier, Jürgen ; Öhlinger, Daniel ; Schmid, Ulrich ; Függer, Matthias ; Nowak, Thomas A Composable Glitch-Aware Delay ModelInproceedings Konferenzbeitrag 22-Jun-2021
4Maier, Jurgen ; Hartl-Nesic, Christian ; Steininger, Andreas Simulation-Based Approaches for Comprehensive Schmitt-Trigger AnalysesArtikel Article 2021
5Maier Juergen - 2021 - Proper abstractions for digital electronic circuits A...pdf.jpgMaier, Jürgen Proper abstractions for digital electronic circuits: A physically guided approachThesis Hochschulschrift 2021
6OEhlinger Daniel - 2020 - The involution tool for accurate digital timing and...pdf.jpgÖhlinger, Daniel ; Maier, Jürgen ; Függer, Matthias ; Schmid, Ulrich The involution tool for accurate digital timing and power analysisArticle Artikel Sep-2020
7Paulweber, Philipp ; Maier, Jürgen ; Cortadella, Jordi Unified (A)Synchronous Circuit DevelopmentPräsentation Presentation2019
8Maier Juergen - 2019 - Efficient Metastability Characterization for...pdf.jpgMaier, Jürgen ; Steininger, Andreas Efficient Metastability Characterization for Schmitt-TriggersInproceedings Konferenzbeitrag 2019
9OEhlinger Daniel - 2019 - The Involution Tool for Accurate Digital Timing and...pdf.jpgÖhlinger, Daniel ; Maier, Jürgen ; Függer, Matthias ; Schmid, Ulrich The Involution Tool for Accurate Digital Timing and Power AnalysisInproceedings Konferenzbeitrag 2019
10Maier Juergen - 2019 - Transistor-Level Analysis of Dynamic Delay Models.pdf.jpgMaier, Jürgen ; Függer, Matthias ; Nowak, Thomas ; Schmid, Ulrich Transistor-Level Analysis of Dynamic Delay ModelsInproceedings Konferenzbeitrag 2019
11Paulweber, Philipp ; Maier, Jürgen ; Cortadella, Jordi Unified (A)Synchronous Circuit DevelopmentPreprint Preprint 2019
12Fan, Chuchu ; Meng, Yu ; Maier, Jürgen ; Bartocci, Ezio ; Mitra, Sayan ; Schmid, Ulrich Verifying nonlinear analog and mixed-signal circuits with inputsKonferenzbeitrag Inproceedings 2018
13Fuegger Matthias - 2018 - A Faithful Binary Circuit Model with Adversarial Noise.pdf.jpgFügger, Matthias ; Maier, Jürgen ; Najvirt, Robert ; Nowak, Thomas ; Schmid, Ulrich A Faithful Binary Circuit Model with Adversarial NoiseInproceedings Konferenzbeitrag 2018
14Maier, Jürgen Modeling the CMOS Inverter using Hybrid SystemsBericht Report 3-Jan-2017
15Maier, Jürgen Modeling III-V semiconductor interfaces at an atomistic level using empirical potentialsThesis Hochschulschrift2016
16Maier, Jürgen ; Detz, Hermann Atomistic modeling of interfaces in III-V semiconductor superlatticesArtikel Article 2016
17Steininger Andreas - 2016 - The Metastable Behavior of a Schmitt-Trigger.pdf.jpgSteininger, Andreas ; Maier, Jürgen ; Najvirt, Robert The Metastable Behavior of a Schmitt-TriggerInproceedings Konferenzbeitrag 2016
18Steininger Andreas - 2016 - Does Cascading Schmitt-Trigger Stages Improve the...pdf.jpgSteininger, Andreas ; Najvirt, Robert ; Maier, Jürgen Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior?Inproceedings Konferenzbeitrag 2016
19Detz, Hermann ; Maier, Jürgen ; Strasser, Gottfried Atomistic Modeling of Interfacial Strain in III-V HeterostructuresKonferenzbeitrag Inproceedings2015
20Maier, Jürgen ; Detz, Hermann ; Strasser, Gottfried Atomistic Interface Modeling in III-V Semiconductor SuperlatticesPräsentation Presentation2015

Contributing Publications Mitbeteiligte Publikationen

Results 1-1 of 1 (Search time: 0.001 seconds).

PreviewAuthor(s)TitleTypeIssue Date
1Wiedemann Sebastian Michael - 2023 - go2async A high-level synthesis tool for...pdf.jpgWiedemann, Sebastian Michael go2async: A high-level synthesis tool for asynchronous circuits based on click-elementsThesis Hochschulschrift 2023