Proper abstractions for digital electronic circuits: A physically guided approach

Abstract

Over the last decades, major improvements in handling semiconductor materials enabled engineers to realize larger and faster digital circuits. The resulting increase in complexity had, however, negative effects on verification: Although nowadays highly accurate models of the main physical processes, which govern the behavior of a circuit, are available, the size and complexity of these models makes it impossible to finish simulations/computations in reasonable time. One possible solution is to introduce abstractions, which have the goal to reduce the verification effort by hiding certain details while preserving accuracy. Naturally, developing proper abstractions is a very challenging task: Too little or the wrong information provide an incomplete picture while excessive models tend to be slow. In this thesis, we study proper abstractions for digital electronic circuits. In our opinion, the best results are achieved by (i) understanding the underlying physical behaviors and (ii) picking appropriate abstract models and parameters based on the gained insights. Overall, we aim at achieving reliable models, which provide high coverage and accuracy at low verification efforts. To achieve this goal, we thoroughly studied the following domains: (1) We describe the analog behavior of various logic gates based on physically inspired simplified transistor equations. (2) We analyze and extend an existing delay estimation method, i.e., we identify several shortcomings, provide proper explanations and develop suitable extension.(3) Finally we run an in-depth analysis of a Schmitt Triggers susceptibility to metastability. From the answers we obtained we can conclude that there is no “silver bullet” w.r.t. modeling abstractions. Every approach is unique in some respect and thus requires a careful analysis of the governing physical behavior to achieve the optimal performance, accuracy and coverage.