Analog filters in nanometer CMOS

Abstract

This thesis examines analog filter design in digital nanometer CMOS technology. Major drive developing analog circuits in digital CMOS technology is the idea of system on chip. In a system on chip all important parts of a system are integrated onto one chip. Although the main parts of such a system on chip are digital function blocks, some blocks remain analog like DAC, ADC, and rf-frontends. Hence, analog design is still necessary in a digital optimized CMOS technology. Two different filter structures are introduced for different applications. The first is a current-mode filter for a transmit path in a software defined radio system. The filters are based on cross-coupled current-mode integrators and low-pass filters. Three 3rd-order current-mode Butterworth filters are designed with the focus on chip-area saving techniques. A capacitance multiplication strategy for fully differential current-mode low-pass filters is developed and an enlargement of 30% of the effective capacitance is achieved. In a comparison to the state-of-the-art it is shown, that the three filter designs are competitive to existing current-mode filters in literature.<br />The second filter design is part of a receiving path of DVB-H devices.<br />It is a 1st-order operational amplifier RC low-pass filter having a gain of 40dB. Three different multi-stage operational amplifiers with feed-forward are presented. High gain-bandwidth products are achieved at a respectable load capacitance. The comparison to the state-of-the-art gives good figures of merit of the presented operational amplifiers despite of limiting factors in nanometer CMOS technology. The first-order Butterworth low-pass filters in the DVB-H receiver are built using the introduced operational amplifiers. The resulting filter performance is moderate because of the power consuming high gain-bandwidth product operational amplifiers. They are needed to reduce the distortions and intermodulations in the filter base-band. A mixer-filter combination is also presented by using the last operational amplifier. The characteristic of the design is the supply voltage of 2.5V in 65nm CMOS technology, which is essential for low non-linearities. The operational amplifier uses cascoding to ensure the voltage limits of the transistors.