Contributions to efficiency and robustness of quasi delay-insensitive circuits

Abstract

In the field of digital integrated circuits asynchronous and especially quasi delay-insensitive (QDI) designs are known to have a high robustness against process, voltage and temperature variations – an increasingly desired property. This is because for QDI designs only very few timing assumptions and constraints are necessary to guarantee the correct behavior of a circuit, which is in strong contrast to the rigid timing scheme of the traditional synchronous design style. This characteristic key-property opens up many interesting and highly relevant application areas – two of are the focus of this thesis. The inherent robustness against timing variations makes QDI design styles and techniques (i) perfectly suited for constructing delay-insensitive (DI) communication channels for global inter- or intra-chip interconnect and (ii) a promising choice for the design of fault-tolerant systems. The first part of this work is, hence, devoted to the investigation of efficient ways to transmit information in a DI way, as well as the design of interface components that allow the integration of asynchronous circuits in otherwise synchronous systems. We provide a comprehensive analysis of available protocols and data encoding schemes and complement them with our own contributions to the field. The second part, then, explores the fault-tolerance aspects of QDI design. In particular, we analyze the effects of transient faults, investigate fault-mitigation strategies from literature and present and evaluate our own techniques. For that purpose, a comprehensive tool set to generate, analyze and simulate asynchronous circuits has been developed.