Down-sampling mixers in nanometer CMOS

Abstract

This thesis deals with the down-conversion mixer part of receivers for GALILEO/GPS and DVB-H systems. A short introduction to different receiver systems is given with their advantages and disadvantages. The focus lies on down-conversion mixers for 1.5 GHz and 666 MHz RF frequency in narrow band systems. Best suitable for implementing such mixers are low-IF direct conversion receivers to avoid DC offset problems but still use direct conversion to reduce complexity and power consumption of the circuits.<br />During the thesis, several different down-conversion mixer topologies have been implemented and tested. Two versions of bulk mixers, three different modified Gilbert mixers, a micromixer and a passive mixer were implemented. All the designs are realized in the same 65 nm low-power digital CMOS process. The designed circuits should be implemented in fully integrated SoC receivers in a pure digital process to reduce development and fabrication cost. Therefore the technology offers very good digital circuit performance but no analog device extension and therefore very poor analog transistor properties. This poses a hard challenge for the analog front-end implementation. All the different implementations were fabricated by Infineon and measured in our laboratory. The use of only one technology allows a simple comparison.<br />During the work, two new topologies have been implemented, the double bulk mixer and the double Gilbert mixer which both utilize two complementary mixers for current reuse and therefore offer higher gain for the same bias condition. The experimental results show that there is always a trade-off between linearity and gain, as well as between noise performance and power consumption. Many comparable implementations in literature use technologies which are more suitable for analog circuit designs.