<div class="csl-bib-body">
<div class="csl-entry">Platzer, M. (2022). <i>Predictable and performant computer architectures for time-critical systems</i> [Dissertation, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2023.110808</div>
</div>
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dc.identifier.uri
https://doi.org/10.34726/hss.2023.110808
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dc.identifier.uri
http://hdl.handle.net/20.500.12708/175647
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dc.description
Vorhersagbare und leistungsfähige Rechnerarchitekturen für zeitkritische Systeme
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dc.description.abstract
In real-time systems, computing tasks must complete within a certain time limit. Otherwise, the system might fail with potentially catastrophic consequences. Therefore, it is essential to analyze the timing behavior of these tasks in order to guarantee that they will always complete in time. However, the timing analysis of modern systems is complicated by the lack of temporal predictability of both the software and hardware, to the point where a timing analysis is not feasible at all. The more predictable architectures traditionally used in real-time systems are no longer capable of fulfilling the performance requirements of today’s demanding workloads. This work addresses the problem by investigating new computer architectures, in line with current trends, for use in time-critical cyber-physical systems, with the aim of closing the current performance gap between predictable and high-performance platforms. In particular, it presents an instruction filter, which can be integrated into existing processor architectures with the aim of executing temporally predictable software on a wide variety of architectures. Also, it proposes the use of a timing- predictable vector processor in a real-time system, a processor type capable of efficiently executing data-parallel worloads and provides increased predictability without compromising performance. Comprehensive evaluations and comparisons with existing approaches show that both of these contributions are competitive alternatives that improve the choice of suitable platforms and the performance of hard real-time systems for relevant workloads.
en
dc.language
English
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dc.language.iso
en
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dc.rights.uri
http://rightsstatements.org/vocab/InC/1.0/
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dc.subject
real-time systems
en
dc.subject
predictable timing
en
dc.subject
single-path code
en
dc.subject
vector processors
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dc.title
Predictable and performant computer architectures for time-critical systems
en
dc.title.alternative
Vorhersagbare und leistungsfähige Rechnerarchitekturen für zeitkritische Systeme
de
dc.title.alternative
Zusammenfassung in deutscher Sprache
de
dc.type
Thesis
en
dc.type
Hochschulschrift
de
dc.rights.license
In Copyright
en
dc.rights.license
Urheberrechtsschutz
de
dc.identifier.doi
10.34726/hss.2023.110808
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dc.contributor.affiliation
TU Wien, Österreich
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dc.rights.holder
Michael Platzer
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dc.publisher.place
Wien
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tuw.version
vor
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tuw.thesisinformation
Technische Universität Wien
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tuw.publication.orgunit
E191 - Institut für Computer Engineering
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dc.type.qualificationlevel
Doctoral
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dc.identifier.libraryid
AC16802603
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dc.description.numberOfPages
98
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dc.thesistype
Dissertation
de
dc.thesistype
Dissertation
en
tuw.author.orcid
0000-0002-5103-8848
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dc.rights.identifier
In Copyright
en
dc.rights.identifier
Urheberrechtsschutz
de
tuw.advisor.staffStatus
staff
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tuw.advisor.orcid
0000-0002-2495-0778
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item.grantfulltext
open
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item.openairecristype
http://purl.org/coar/resource_type/c_db06
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item.mimetype
application/pdf
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item.openairetype
doctoral thesis
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item.openaccessfulltext
Open Access
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item.languageiso639-1
en
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item.cerifentitytype
Publications
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item.fulltext
with Fulltext
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crisitem.author.dept
E191-01 - Forschungsbereich Cyber-Physical Systems