An integrated 17 GHz transmitter in 0.13 [my]m CMOS for wireless applications

Abstract

This work presents the design and implemtnation of a fully integrated transmitter in 0.13um CMOS technology for the 17GHz ISM band which is intended for future WLAN applications. Major challenges in the design are to provide a high linear output power, handle the high operation frequency and to achieve a high integration scale while keeping the power consumption low. The transmitter is realized by using a so called "sliding IF" double conversion architecture. In contrary to the classical heterodyne conversion, sliding IF topology requires only one VCO. Pros and cons in comparison with other architectures will be discussed in detail. Active and passive integrated components are investigated because understanding of the device characterisitcs turns out as a key requirement to achieve a successful high frequency design.<br />Subsequently, circuit design fundamentals of the buildings blocks are introduced. Finally, the implementation of the transmitter is presented.<br />The functionality of the integrated 17GHz transmitter is demostrated by different measurements. The chip includes VCO, IQ divider, IQ modulator, up conversion mixer and a pre power amplifier with a area of only 0.8x1mm 2. A fully differential ciruit design is implemented. It exhibits a power consumption of 236mW at a supply voltage of 1.5V. The output referred 1dB compression point is 3dBm with a load impedance of 100Ohm.