Reconfigurable Si field-effect transistors with crystalline Al contacts enabling adaptive complementary and combinational logic

Abstract

The remarkable progress in electronics is marked by the continuous miniaturization of device sizes however, the ongoing scaling strategy, is not sustainable in the long term, as physical limits will be reached soon. Further, the increase in data processing requirements and the resulting complexity of signal routing on a chip has posed significant challenges in terms of raised power consumption and diminished reliability. In order to optimize the performance of information processing, it is crucial to introduce novel concepts. One potentially effective strategy involves the advancement of reconfigurable logic or neuromorphic devices. These reconfigurable field-effect transistors (RFETs) are characterized by their dynamic p- and n-channel switching behavior making them highly regarded as a potential breakthrough for future computer systems. RFETs offer the advantage over conventional complementary circuits that the transistor widths of n- and p-FETs do not need to be individually adjusted to achieve equal current densities, that enables the realization of multifunctional devices and dynamically reconfigurable complementary logic gates with a reduced number of devices compared to unipolar transistors. In this regard, this master thesis deals with the fabrication of reconfigurable Field-Effect Transistors (RFET) using a top-down approach on a silicon-on-insulator (SOI) wafer. The thermally induced metal-semiconductor exchange reaction of Al and Si resulting in the formation of the underlying Al-Si-Al heterostructure, is a crucial process for ensuring the reliable and consistent occurrence of an abrupt transition. This exchange reaction process is essential for reproduceable contacts with defined properties. Silicon dioxide (SiO2) serves as the gate dielectric, positioned between the semiconductor channel and the top gates. This material is chosen for its high purity and low charge carrier trapping, resulting in minimal hysteresis in the devices. Through a comprehensive statistical analysis, it is demonstrated that significant advancements have been made in key transistor parameters, such as the symmetry of on-currents from p-FET to n-FET. Moreover, these advancements have resulted in exceptional stability and reproducibility. Consequently, complementary logic gates could be manufactured using cascaded RFETs. The reconfigurability at the circuit level of an inverter comprised of two RFETs on a semiconductor nanostructure was effectively demonstrated. A reconfigurable MIN3-gate capable of dynamic switching between NAND/NOR operations was successfully implemented by integrating only three RFETs. An XOR/XNOR-gate with dynamic switching could be created using just four RFETs. Therefore, the quantity of devices can be decreased in comparison to circuits with traditional transistors. The gates possess a full-swing output voltage and share identical supply and signal voltages, indicating their potential to realize complex circuits and microprocessors with reconfigurable circuits.