Electrical transport in reconfigurable transistors based on the heterogeneous integration of Germanium on a silicon on insulator platform

Abstract

Driven by Moore’s Law, the demand for ever more transistors on integrated circuits has surged to power our digital age. This principle predicts the doubling of transistors approximately every two years, propelling technological advancements. As we approach the physical limits of traditional scaling, beyond Moore technologies and innovative material systems emerge as essential pathways. Their adoption ensures sustained growth, meeting the insatiable computational needs of the future. One approach based on functional diversification is the novel device concept of a doping free reconfigurable field-effect transistor (RFET). These stand out by their ability to dynamically switch between n-type and ptype operation during runtime, hence increasing the functional density of the circuit. Since both operation types are united in one single RFET device, typical channel width variations for p- and n-type in order to achieve similar on-state currents are not possible. The desired symmetry and other crucial device characteristics need to be engineered by the underlying material-system. Considering this, the influence on the electrical behavior of a RFET fabricated out of a pure germanium (Ge) layer on top of either a strained or unstrained silicon wafer stack, exerting different amounts of stress on the channel, are investigated in this thesis. Furthermore, the effect of different gate dielectrics, consisting of pure silicon dioxide (SiO2) or a combination of SiO2 and zircon dioxide (ZrO2), are considered. The respective transistors are fabricated in a top-down fashion out of a Ge on a silicon on insulator (SOI) or Ge on strained silicon on insulator (sSOI) initial wafer, which takes advantage of the electrical properties of Ge like the high charge carrier mobility and small band-gap, while bypassing the difficult and expensive Ge on insulator technology. The required metal-semiconductor-metal heterostructures, in the case of this thesis, the aluminum-Ge-aluminum heterostructure, are formed by thermally activated aluminum (Al) diffusion into the Ge nanosheet, resulting in reproducible, reliable and abrupt transitions. In order to form the SiO2 passivation, a pure silicon (Si) capping layer atop of the Ge layer is dry thermally oxidized, while the ZrO2 high-k dielectric is fabricated by atomic layer deposition (ALD). In this thesis four different types of transistors with an increasing number of top-gates are fabricated. The realized RFETs with either two or three independent top-gates, or Schottky barrier field-effect transistor (SBFET) with one single top-gate are electrically characterized. By extensive temperature dependent bias spectroscopy, important properties of the transistors and underlying material system are determined and compared to other RFETs found in literature. Moreover, the performance of single transistor wired logics consisting of RFETs with four top-gates are analyzed. The goal of this thesis was the realization of Ge based RFETs, which offer enhanced electrical properties considering the Si counterparts. Thereby relatively higher on-state currents of the respective modi and sufficient on-state symmetries were achieved. With the addition of ZrO2 to the gate stack, improvements regarding the On/Off ratio and subthreshold slope were obtained. The material system and RFET structures presented in this thesis highlight the potential for energy-efficient and adaptive circuits in areas such as hardware security and artificial intelligence.