QDI Binary Comparator Networks and their Application in Combinational Logic

Abstract

Binary comparator networks have already been used in quasi delay-insensitive (QDI) circuit design for the construction of completion detectors. This paper demonstrates how they can also be utilized to implement a wide range of Boolean functions for combinational QDI logic blocks. Designing combinational logic for QDI circuits poses several challenges because data must be processed in an encoded form (usually dual-rail) and it must be ensured that the resulting circuits do not contain hazards or orphans. These design constraints impose a considerable hardware overhead on the resulting circuits. Hence, over the years numerous design and optimization strategies have been proposed. We show that our comparator-network-based construction approach yields promising results for certain types of functions compared to other common QDI design styles.