Highly-Sensitive Integrating Optical Receiver with Large PIN Photodiode

Abstract

This paper presents a highly-sensitive monolithic optoelectronic receiver in 180nm CMOS. An integrating frontend with noise matching via an negative Miller capacitance is proposed, to reduce the power penalty imposed by large PIN photodiodes (PDs). Three new multi-dot PIN PDs are integrated with the front-end. At a wavelength of 642nm and reverse bias of 8V, their responsivity (capacitance) is 0.38A/W (29 fF), 0.36A/W(33 fF), and 0.43A/W(123 fF), respectively. Compared to our previous integrating PIN receivers, the light-sensitive area is up to 30 times larger. At a supply voltage of 1.8V, wavelength of 642nm, bit rate of 20 Mbit/s, and reference BER = 2 · 10⁻³, the prototype receiver achieves a sensitivity of -55.4dBm for the first PD, -56.5dBm for the second PD, and -53.4dBm for the third PD. The best sensitivity equals a distance of only 21.2dB to the quantum limit.