<div class="csl-bib-body">
<div class="csl-entry">Demir, A., & Ulus, D. (2026). Multi-Property Temporal Logic Monitoring. In B. Dutertre & B. Könighofer (Eds.), <i>Proceedings of the 26th Conference on Formal Methods in Computer-Aided Design – FMCAD 2026</i> (pp. 210–219). TU Wien Academic Press. https://doi.org/10.34727/2026/isbn.978-3-85448-093-8_27</div>
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Runtime verification enables checking temporal logic specifications over individual execution traces and offers a scalable alternative to exhaustive formal verification. In practice, systems must satisfy dozens to hundreds of temporal properties simultaneously; however, existing approaches monitor each property in isolation, resulting in redundant computation and limited scalability. In this work, we present an online multi-property monitoring framework that compiles past-time LTL and MTL specifications into a shared directed acyclic graph of subformulas with one output per property. Unlike prior approaches that construct monitors independently, our method extends compositional sequential network-based temporal logic monitor construction to a shared setting, enabling reuse of intermediate results across properties while preserving their individual structure. Central to our approach is a data-oriented execution model based on an arena-allocated, double-buffered layout that stores intermediate results for each subformula in compact, contiguous memory. This design favors spatial locality and enables incremental updates with minimal overhead. Experimental results demonstrate per-property throughput improvements of 2× to 4.5× and 6× to 12× in multi-property configurations compared to conventional single-property monitoring, enabling scalability to large specification sets and deployment in high-performance and resource-constrained systems.
en
dc.language.iso
en
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dc.rights.uri
http://creativecommons.org/licenses/by/4.0/
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dc.subject
formal methods
en
dc.subject
computer-aided system design
en
dc.subject
hardware and system verification
en
dc.title
Multi-Property Temporal Logic Monitoring
en
dc.type
Inproceedings
en
dc.type
Konferenzbeitrag
de
dc.rights.license
Creative Commons Namensnennung 4.0 International
de
dc.rights.license
Creative Commons Attribution 4.0 International
en
dc.identifier.doi
10.34727/2026/isbn.978-3-85448-093-8_27
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dc.contributor.editoraffiliation
Amazon Web Services
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dc.contributor.editoraffiliation
Graz University of Technology (Graz, AT)
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dc.relation.isbn
978-3-85448-093-8
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dc.description.volume
7
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dc.description.startpage
210
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dc.description.endpage
219
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dc.rights.holder
Arınç Demir and Dogan Ulus
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dc.type.category
Full-Paper Contribution
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dc.relation.eissn
2708-7824
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tuw.booktitle
Proceedings of the 26th Conference on Formal Methods in Computer-Aided Design – FMCAD 2026
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tuw.peerreviewed
true
-
tuw.relation.ispartof
10.34727/2026/isbn.978-3-85448-093-8
-
tuw.relation.publisher
TU Wien Academic Press
-
tuw.book.chapter
27
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tuw.researchTopic.id
I1
-
tuw.researchTopic.id
I2
-
tuw.researchTopic.id
C5
-
tuw.researchTopic.name
Logic and Computation
-
tuw.researchTopic.name
Computer Engineering and Software-Intensive Systems
-
tuw.researchTopic.name
Computer Science Foundations
-
tuw.researchTopic.value
40
-
tuw.researchTopic.value
40
-
tuw.researchTopic.value
20
-
tuw.publication.orgunit
E000 - Technische Universität Wien
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dc.identifier.libraryid
AC17999029
-
dc.description.numberOfPages
10
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tuw.relation.ispartoftuwseries
Conference Series: Formal Methods in Computer-Aided Design