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Record link: 
http://hdl.handle.net/20.500.12708/55128
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Title: 
Measuring SET pulsewidths in logic gates using digital infrastructure
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Citation: 
Veeravalli, V. S., Steininger, A., & Schmid, U. (2014). Measuring SET pulsewidths in logic gates using digital infrastructure. In Fifteenth International Symposium on Quality Electronic Design. 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA, Non-EU. https://doi.org/10.1109/isqed.2014.6783331
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Publisher DOI: 
10.1109/isqed.2014.6783331
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Publication Type: 
Inproceedings - Full-Paper Contribution
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Authors: 
Veeravalli, Varadan Savulimedu 
Steininger, Andreas 
Schmid, Ulrich 
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Organisational Unit: 
E191-02 - Forschungsbereich Embedded Computing Systems 
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Published in: 
Fifteenth International Symposium on Quality Electronic Design 
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Date (published): 
2014
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Event name: 
15th International Symposium & Exhibit on Quality Electronic Design 
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Event date: 
10-Mar-2014 - 12-Mar-2014
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Event place: 
Santa Clara, USA, Non-EU
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Number of Pages: 
7
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Peer reviewed: 
Yes
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Abstract: 
We present a purely digital infrastructure for measuring SET pulsewidths in logic gates. Such a facility is crucial for experimentally studying radiation sensitivity and SET propagation of a circuit. Our digital-only implementation facilitates measurement within a standard cell CMOS chip, without the need of any analog or customized circuitry on-chip. Besides high resolution and area efficiency, a...
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Research Areas: 
Computer Engineering and Software-Intensive Systems: 100%
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Science Branch: 
Informatik
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Appears in Collections:
Conference Paper

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