Sorting Network based Full Adders for QDI Circuits

Abstract

In this paper we focus on the efficient design of ripple-carry adders (RCAs) in quasi delay-insensitive (QDI) logic. We review approaches from the literature that are suitable for implementation in modern CMOS technology and identify their weaknesses. Based on these insights we propose novel full adder designs that are built around binary sorting networks. In order to maintain the timing robustness of QDI logic, a thorough management of gate orphans is necessary. Our analysis gives evidence that the proposed circuits are more area efficient than existing approaches, while still maintaining a comparable performance in terms of average delay.