Ni, L., Pudukotai Dinakarrao, S. M., Song, Y., Gu, C., & Yu, H. (2016). A Zonotoped Macromodeling for Eye-Diagram Verification of High-Speed I/O Links With Jitter and Parameter Variations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(6), 1040–1051. https://doi.org/10.1109/tcad.2015.2481873
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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ISSN:
0278-0070
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Date (published):
Jun-2016
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Number of Pages:
12
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Peer reviewed:
Yes
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Keywords:
Electrical and Electronic Engineering; Software; Computer Graphics and Computer-Aided Design; reachability analysis; parallel processing; Monte Carlo simulation; Monte Carlo methods; analogue circuits; integrated circuit modelling
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Abstract:
It is challenging to efficiently evaluate the performance bound of high-precision analog circuits with input and parameter variations at nano-scale. With the use of zonotope to model uncertainty of input data pattern (or jitter) and multiple parameters, a reachability-based verification is developed in this paper to compute the worst-case eye-diagram. The proposed zonotope-based reachability analysis can consider both spatial and temporal variations in one-time simulation. Moreover, a nonlinear zonotoped macromodeling is further developed to reduce the computational complexity. Performance bound for I/O links considering the parameter variations are evaluated. In addition, the eye-diagrams are generated by the proposed zonotoped macromodel for performance evaluation considering both temporal and spatial variations. As shown by experiments, the zonotoped macromodel achieves up to 450× speedup compared to the Monte Carlo simulation of the original model within small error under specified macromodel order for high-speed I/O links eye-diagram verification.
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Research Areas:
Logic and Computation: 30% Modelling and Simulation: 70%
