SET Hardened Derivatives of QDI Buffer Template

Abstract

As critical charges become smaller due to technology advancement, Single Event Transients (SET's) become more threatening to circuits. Quasi Delay-Insensitive (QDI) circuits are tolerant against timing issues, but they tend to be more sensitive towards transients - and hence SET's - in the value domain. This can be somewhat mitigated, without sacrificing their delay insensitivity, by shortening their sensitive data acceptance windows. In this paper we investigate these sensitive areas in search of possible ways to specifically harden buffer stages, as these are elementary for building asynchronous pipelines and play a major role in the manifestation of an SET as a Single Event Upset (SEU). Inspired from existing work in the literature, we propose a buffer template called 'Dual CD IN/OUT Interlock WCHB' that is basically a hybrid approach to smartly shorten the sensitive window. It reduces the cases where existing approaches fail by up to 5% magnitude. Further investigation suggests some improvement in the design, namely the 'Dual CD IN/OUT Interlock WCHB Simplified' which leads to up to 44% area savings without effecting the core resilience. The enhancements are verified in simulation with realistic circuits like Multiplier, ALU, and FIFO under a timing model from the NanGate 15nm library.