Seyedfaraji, S., Mesgari, B., & Rehman, S. (2022). AID: Accuracy Improvement of Analog Discharge-Based in-SRAM Multiplication Accelerator. In 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 873–878). https://doi.org/10.23919/DATE54114.2022.9774748
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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ISBN:
978-3-9819263-6-1
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Date (published):
1-Jan-2022
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Event name:
Design, Automation and Test in Europe Conference | The European Event for Electronic System Design & Test
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Event date:
14-Mar-2022 - 23-Mar-2022
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Event place:
ONLINE via VIRTUAL PLATFORM, Belgium
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Number of Pages:
6
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Keywords:
Low Power; Neural Network; Process in Memory; SRAM
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Abstract:
This paper presents a novel circuit (AID) to improve the accuracy of an energy-efficient in-memory multiplier using a standard 6T -SRAM. The state-of-the-art discharge-based in-SRAM multiplication accelerators suffer from a non-linear behavior in their bit-line (BL, BLB) due to the quadratic nature of the access transistor that leads to a poor signal-to-noise ratio (SNR). In order to achieve linearity in the BLB voltage, we propose a novel root function technique on the access transistor's gate that results in accuracy improvement of on average 10.77 dB SNR compared to state-of-the-art discharge-based topologies. Our analytical methods and a circuit simulation in a 65 nm CMOS technology verify that the proposed technique consumes 0.523 pJ per computation (multiplication, accumulation, and preset) from a power supply of 1V, which is 51.18% lower compared to other state-of-the-art techniques. We have performed an extensive Monte Carlo based simulation for a 4×4 multiplication operation, and our novel technique presents less than 0.086 standard deviations for the worst-case incorrect output scenario.
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Research Areas:
Logic and Computation: 80% Computer Engineering and Software-Intensive Systems: 20%