Hardware acceleration for line segment detection

Abstract

Line segment detection is an important preprocessing step in Computer Vision applications. However, most of the existing algorithms are designed to be run on general purpose processors with high power consumption and will not achieve high framerates on low-cost embedded hardware. Furthermore, these algorithms are usually not suited for hard real-time applications. In this thesis, two novel methods are proposed: The first is an optimization for the Line Segment Detector (LSD), a widely used line segment detection algorithm, using a lookup table (LUT). We show that this optimization decreases the processing time by 13:08% on average, up to a maximum of 28:8%, while keeping 99:84% of the output identical. Secondly, a novel line segment detection algorithm is proposed, designed for implementation on field-programmable gate arrays (FPGAs). An implementation of this algorithm on a Xilinx XC7Z015 FPGA runs at 100 MHz while using less than 10% of the available on-chip resources. Images in 640x480 resolution can be processed at 325.5 frames per second and a latency of 32.27 us, while for the maximum resolution of 1080p (1920x1080) 48.23 frames per second can be achieved with an latency of 96.27 us. Additionally, the latency and throughput of the algorithm are only depending on the image resolution, but not on the image contents, making it compatible with hard real-time environments. The algorithm beats existing FPGA-based line segment detectors in terms of latency, while using less on-chip resources and achieving a comparable detection quality.