Concepts for virtual prototyping of distributed embedded systems

Abstract

As computers systems continue to grow rapidly in both complexity and scale, developers need improved techniques in design and particular in verification of these systems. State-of-the-art hardware/software co-verification methodologies are pushed to their limits in regards of simulation performance and flexibility. Virtual Prototyping is far away from being well established in electronic design automation, consequently neither clear understanding of the topic nor standard way of practice is existent. This dissertation contributes in this field as it presents concepts for building a flexible simulation environment that allows for appliance on various design abstraction levels, ranging from the functional level to the Register Transfer Level (RTL).<br />Furthermore, this work provides a solution to the problem of simulation performance that is predetermined when complex embedded systems shall be verified on the RTL, together with software workloads for distributed algorithms that far exceed usual simulation run-times of a few milliseconds.<br />The theoretical part is consolidated by the demonstration of a virtual prototype based on a real-world distributed embedded system. Detailed simulation results and performance measures complete this dissertation.