Numerical methods for three-dimensional selective epitaxy and anisotropic wet etching simulations

Abstract

The development of semiconductor device fabrication techniques which operate on complex three-dimensional topographies strongly benefits from technology computer-aided design (TCAD). Particularly important for intricate topographies and at the center of the research presented in this thesis are selective epitaxial growth and anisotropic wet etching processes, which are essential for fabricating fin field-effect transistors (fin FETs), substrate patterning for efficient light emitting diodes (LEDs), and micro-electro-mechanical systems (MEMS). The introduction of alternative materials to silicon (e.g., silicon carbide and sapphire) with their unique processing requirements further intensifies the need for specialized TCAD algorithms and models. In this thesis, to set the stage, the fundamental phenomena causing strong anisotropy in selective epitaxy and wet etching are presented and various modeling approaches are reviewed. Since continuum modeling approaches are particularly attractive for TCAD, process simulations based on the level-set method are discussed in depth. However, the computational treatment of anisotropic processes with level-sets poses several challenges involving numerical stability and sensitivity to the accuracy of the geometry description. Hence, numerical methods for the level-set method, namely a novel finite difference Stencil Lax-Friedrichs scheme and the deposition top layer method, which are tailored to selective epitaxy and anisotropic wet etching are proposed and assessed with respect to high accuracy and physical relevance. The thus advanced level-set method enables the simulation of strongly anisotropic steps manifesting in a variety of state-of-the-art semiconductor fabrication processes, including source-drain engineering of FETs and LEDs. The involved crystalline materials (e.g., silicon-germanium, silicon carbide, and sapphire) exhibit different crystal symmetries and induce complex topographies, which need to be accounted for by computational methods. Hence, a general etch/deposition rate interpolation procedure which respects the associated symmetry operation is proposed and evaluated. Moreover, a continuum model for anisotropic wet etching of sapphire with phosphoric and sulfuric acid, which covers different etchant mixtures and etching temperatures is presented. The capability of the modeling approach is demonstrated by comparing the simulation results with experimental observations from the literature. Furthermore, closely coupled process and device simulations are investigated, which allow to link process parameters with the resulting device characteristics. By way of example, the impact of post-implantation annealing parameters on silicon carbide power transistor characteristics are studied. Additionally, the sapphire wet etching model is utilized to study geometrically patterned gallium nitride-based LED structures and characterize the light extraction efficiency with ray-tracing calculations. These simulations reveal the subset of the process parameter space resulting in optimal device characteristics and thus corroborate the merits of level-set based process simulation.