ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic

Abstract

Due to their flexible data accepting windows Quasi Delay-Insensitive (QDI) circuits are susceptible to environmental effects such as single event transients (SETs). Their mode of operation often demands that the combinational logic of such circuits contains storage elements in the form of Muller C-element (MCE)s. This fact makes it likely for an SETs to be converted into an single event upset (SEU). Nevertheless, most of the available approaches in literature focus on hardening the butter elements between combinational logic blocks to mitigate the effects of SETs with less emphasis on the logic itself. In this work, we first review existing techniques addressing SETs in combinational logic. We analyze and compare them to a non-resilient basic QDI circuit template. We conclude that these techniques are not effective compared to this basic template because the addition of extra circuitry increases the susceptibility of the overall circuit towards SETs. Some of these techniques are only valid with extra assumptions, one is, exempting the mitigating circuit part from fault injection. Another main limitation is concerning the way in which the circuits flush out faults in the combinational logic. The proposed techniques can easily lead to a violation of the handshake protocol by forcing all combinational signals to zero, which may introduce an additional null phase depending on the next stage. After thorough analysis, we present a technique to flush the erroneous value within the combinational logic while maintaining the remaining part of combinational logic. This flushing does not require extra combinational cycles for re-computing the logic value. We combine our novel flushing approach with a resilient butter style to make the overall circuits highly resilient towards SETs. To facilitate a fair comparison we also utilize this resilient butter template with other combinational logic flushing techniques. For the evaluation of the results, we simulate all techniques with a 16-bit multiplier circuit realized with the NanGate 15nm library. The extensive fault injection experiments show the resilience of our novel combinational logic flushing approach.