Utilizing and Extending the Inherent Fault Tolerance Properties of Asynchronous QDI Circuits

Abstract

Timing variation is one of the main concerns in clocked circuits. The inherent self-timed property of asynchronous circuits can efficiently address this problem and convince the community to explore its other veiled benefits. The Quasi Delay-Insensitive (QDI) class of circuits, due to its flexible timing compared to synchronous circuits and its realization structure, represents a good trade-off. However, its event-driven nature, while being instrumental for the desired adaptive timing, makes it prone to other environmental effects such as single event transients (SETs). This is because connected modules are free in their generation and consumption timing of data, which makes waiting windows unpredictable and leaves the circuit remaining open to any change regardless of the source. In this thesis, we investigate the main three parts of QDI circuits – storage element (buffer template), combinational logic and conditional control element – during these windows under the influence of SETs. The buffer template of a QDI circuit is based on a basic asynchronous element called Muller C-element (MCE) (or other gates with hysteresis). Its working principle comprises two modes, combinational mode when all inputs match, meaning the output is strongly indicated by the inputs, and storage mode when the output is defined by the internal storage loop of the MCE. In storage mode the MCE is susceptible to SETs from input as well as output. The alternation between these modes and consequently its susceptible window length is depended on its connected environment, source and sink. We analyze the behavior of QDI circuits in relation to SETs for variable speed of source and sink. For a first understanding, we start our investigations with an empty pipelined circuit, as the buffer is the active part in the handshaking, and it is responsible for converting an SET into an single event upset (SEU). We propose several techniques to improve the resilience of the buffer template against SETs. Basically these techniques utilize the handshake cycle information to shorten the armed (sensitive) windows of the buffers. The results confirm that our proposed enhancements make the circuits more resilient against SETs. We also examine the effects of MCEs in the combinational part separately and strive to resolve transient issues before they reach the buffer elements. Using a pipelined multiplier circuit for our analysis we analyze two respective state-of-the-art techniques and finally propose an improved technique which, upon detection of a transient within the combinational logic, (1) freezes the data latching activity of buffer, and (2) leverages the QDI nature of the circuit to selectively flush all those MCEs that are supposed to be zero during this handshake cycle. Promising experimental results back the theoretical concepts of our approach.The conditional control elements of QDI circuits also comprise MCEs. We modify these in a way that the current handshake information is used by the unselected path to nullify transitions caused by SETs. The experimental analysis shows that these enhancements contribute well to the resilience of the circuit. In general, we strive to make best use of the intrinsic fault detection capabilities in QDI circuits while considering other trade-offs. The novelty of our work lies in addressing concerns in detail that arise when the environment behaves abnormally in a QDI circuit. As each variation reveals its own problems and benefits on top of the novel techniques we propose for mitigating SET effects, we need to carefully adjust suitable approaches. The ultimate objective is to attain a high level of resilience against SETs, also utilizing their inherent delay insensitivity while minimizing redundancy. The results confirm that we successfully achieved better resilience than the state-of-the-art approaches.