Design and characterization of CMOS avalanche photodetectors

Abstract

Detecting weak optical signals is crucial across diverse opto-electronic applications, from time-of-flighsensors and quantum cryptography to optical wireless communication and medical diagnostics via optical tomography. The avalanche photodiodes employ the avalanche multiplication effct, allowing for signal amplification offerin high sensitivity, thereby enabling the detection of weak optical signals across a range of applications. These photodiodes, depending on the operating voltage, can either provide moderate and linear avalanche amplification which is called APD, or work in Geiger mode and provide a gain in the range of millions, known as SPAD. In addition, the use of a CMOS process for the production of integrated avalanche photodiodes with electronic circuitry for read-out and signalprocessing reduces the influenc of parasitic effcts, and furthermore offer a cost-effctive production.Accordingly CMOS avalanche photodiodes are attractive candidates as optical detectors in many optical systems that require low-light detection.This thesis begins by presenting a photon detection probability (PDP) model for SPAD, which is very valuable for the development and optimization of SPADs while avoiding time-consuming exper-imental investigations. The dependence of SPAD’s PDP on the distribution of the electric fiel inside the structure and also the propagation behavior of the irradiated light to reach the photo-sensitive area of the photodiode are investigated and discussed based on the presented model.Conventional design approaches towards CMOS-integrated avalanche photodiodes (APDs and SPADs)rely on planar n+/p-well or p+/n-well junctions. In these structures, the presence of physical guardrings to avoid a premature edge breakdown decreases the fil factor, defind as the ratio of the photo-sensitive area to the total device area. My research delves into investigating the implementation ofvirtual guard rings to enhance the fil factor within such structures. In addition to the low fil factor and limited scalability of these structures, they generally exhibit a trade-of between bandwidth and responsivity, notably observed in the long-wavelength range when they operate in the linear mode (APD operation mode).To address these limitations, I implement the field-lin crowding concept to design a new APD by employing a small n+/n-well structure fabricated in a standard CMOS process without process modification This structure provides a maximum bandwidth of 1.6 GHz with a responsivity of 32 A/W at a wavelength of 675 nm and at an operating voltage of 67 V while having a high sensitive-area to total-area ratio. Its scalability while retaining sensitivity and offerin a large fill-facto makes it attractive for array sensor applications. Further characterization in the near-infrared range and investigation into design parameter effcts on its performance are presented.However, the high operational voltage of these diodes can present integration challenges with elec-tronic circuits in some CMOS technologies. Therefore, this study introduces a novel CMOS-integrated dot avalanche photodiode, demonstrating comparable performance at significantl lower operating voltages compared to the field-lin crowding APD. Additionally, my research proposes a n+/p-well multi-dot structure, comprising an array of individual dots with a shared anode. This innovative de-sign facilitates the expansion of the active area while upholding performance, there by positioning themulti-dot APD as a promising solution for applications necessitating a larger light-sensitive area. Furthermore, leveraging the advantage of decoupling the P/N junction area from the light-sensitive area in such structures enables designing a high light-sensitive-area photodiode with a relatively small capacitance.