Fazekas, K., Pollitt, F., Fleury, M., & Biere, A. (2024). Incremental Proofs for Bounded Model Checking. In MBMV 2024 : 27. Workshop (pp. 133–143). http://hdl.handle.net/20.500.12708/211103
E192-04 - Forschungsbereich Formal Methods in Systems Engineering
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Published in:
MBMV 2024 : 27. Workshop
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ISBN:
978-3-8007-6267-5
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Date (published):
19-Jun-2024
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Event name:
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2024)
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Event date:
14-Feb-2024 - 15-Feb-2024
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Event place:
Kaiserslautern, Germany
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Number of Pages:
11
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Peer reviewed:
Yes
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Keywords:
SAT-based BMC; Incremental SAT solving; Proof Checking
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Abstract:
Bounded model checkers show the validity of a property of a hardware or software system to hold up to a certain bound by solving a sequence of related Boolean satisfiability (SAT) problems. An incremental SAT solver, a tool often used by such model checkers, can exploit similarities between these consecutive SAT problems. By avoiding repeated work incremental solving is much more efficient. To increase the trustworthiness of a model checker, it is however important to provide assurance about the correctness of its underlying solving engine. Though modern SAT solvers are expected to produce an independently verifiable certificate when a formula is unsatisfiable, incremental SAT solving involves multiple formulae under different temporary assumptions. In this paper we propose a new proof format for SAT solvers applicable to incremental use cases and demonstrate the viability of it in the context of bounded hardware model checking.
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Project title:
Inkrementelles SAT und SMT für skalierbare Verifikation: T 1306-N (FWF - Österr. Wissenschaftsfonds)
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Research Areas:
Logic and Computation: 40% Computer Engineering and Software-Intensive Systems: 40% Computer Science Foundations: 20%