Investigating floating gate insertion into ferroelectric Schottky barrier field-effect transistors for neuromorphic computing

Abstract

The recent rise of artificial intelligence (AI) has been facilitated by the ongoing developments in semiconductor technologies. Current implementations rely on graphical processing units (GPUs), while future performance improvements are limited by the slowing down of Moore’s law and the “von Neumann bottleneck”. In particular, the latter poses a hard barrier to the reduction of power consumption for the existing hardware platforms. A suitable alternative direction appears to be neuromorphic computing, utilizing emerging memory devices, like the ferroelectric field effect transistors (FeFETs), to mimic neurons and synapses that are the basic building blocks of the human brain. Thanks to the recent discovery of HZO, FeFETs can be efficiently implemented in established frameworks. The reconfigurable FET (RFET), which does not use doped regions, but exploits the electrostatic modulation of Schottky Barriers to determine the charge carrier type, represents a feasible alternative that can provide more functionality in a reduced wafer area. Evolving this concept towards a ferroelectric-based neuromorphic architecture is extremely promising for the realization of extremely flexible and power-efficient AI networks. Founded on an already established ferroelectric SBFET (FeSBFET) process, this thesis studies how the introduction of a TiN floating gate (FG) layer in between the SiO layer and the HZO impacts the switching behavior. It is expected that the FG insertion will make the devices less trap-dependent. Within this work, a wet-etching process is developed for the pattering of thin TiN layers. Analysis of the final gate structure employing atomic force microscopy (AFM) and transmission electron microscopy (TEM) indicates an excellent control of the performed processing. Electrical measurements of test structures validate the ferroelectricity of the deposited HZO and the correct formation of SBs beneath the top gate (TG). Transfer characteristics of the FG FeSBFET devices show a shift of ±1.4 V depending on the sweeping direction. A simple mathematical model derived from the one describing non-ferroelectric FGFETs used in flash storage devices allows the estimation of the effective charges in the FG layer. These charges, which determine the device characteristics, are the result of the balance between the charges coming from the ferroelectric polarization and those injected into the layer. It is observed that, in the case of slow sweeping, a majority of injected charges are present. Pulsed measurements with varying pulse times indicate that after 6 ms, enough charges are injected to enable the ferroelectric switching mechanism, which, in turn, reduces the injection rate.The promising characteristics of the fabricated devices for future application in neuromorphic computing platforms are clearly demonstrated by the long-term potentiation (LTP) and long-term depression (LTD) curves extracted from the pulsed measurements. Adaptation of the surface ratio of the involved layers is needed to bring the pulse time in a similar range as what is displayed by other neuromorphic device concepts currently under investigation.