Low junction capacitance PIN and avalanche photodiodes in 180 nm CMOS

Abstract

This paper presents a comprehensive study of low-capacitance PIN photodiodes and avalanche photodiodes (APDs) implemented in 180 nm CMOS. The approach utilizes the dot-shaped cathode design to achieve hemispherical space-charge regions, effectively decoupling the photosensitive area from the junction capacitance and thus optimizing device performance for optical communication applications. Key device parameters—capacitance, bandwidth, light-sensitive area, and excess noise—are characterized and compared. All devices were fabricated on the same wafer for direct performance comparison. The presented dot-cathode photodiodes achieve significantly reduced total and normalized (per area) capacitance without compromising bandwidth compared to planar APDs. Among them, electric field line crowding (EFLC) based APDs demonstrate superior performance with the highest responsivity (0.4A W⁻¹ @ 642 nm), lowest capacitance per area (1.58 aF μm⁻²), and low excess noise (F = 1.8 @ M = 10) with a bandwidth of 1.6 GHz. In contrast, the presented N+/P-well (NPPW) based APDs exhibit high excess noise making them unsuitable for data receiver applications. Notably, the only PIN device presented, uniquely operates in PIN mode with maximum bandwidth, while all other devices show reduced bandwidth unless they are operated in APD mode.