SeAL: A Provably Complete Fault-Injection Tool for Asynchronous Circuits

Abstract

As fault tolerance becomes an increasingly critical concern in digital circuit design, asynchronous architectures offer promising robustness against faults like timing variations. Although prior studies have investigated circuit fault behavior using empirical techniques, a comprehensive analysis grounded in formal methods has remained largely unexplored.In this paper, we present the tool SeAL (Sensitivity Ana-lyzer for Asynchronous Logic) that enables formal modeling, simulation, and systematic fault injection for both transient and permanent fault types. Leveraging provably complete algorithms, our tool reliably identifies susceptibility windows for all signals in a circuit, i.e., critical temporal regions where circuit behavior may deviate due to injected faults. It supports trace-based simulation, fault equivalence checking, and output analysis to reveal vulnerabilities that are difficult to detect through traditional testing. The tool’s modular architecture allows seamless integration with circuit descriptions and supports both empirical experimentation and formal verification workflows. We demonstrate its capabilities through case studies on quasi delay-insensitive (QDI) components, highlighting its value in rigorous fault resilience evaluation, and show that the tool can also be used to analyze synchronous circuits, allowing one to systematically compare design paradigms with respect to resilience.